* Re: [PATCH v6] target/riscv: Add isa extenstion strings to the device tree
2022-03-16 17:57 [PATCH v6] target/riscv: Add isa extenstion strings to the device tree Atish Patra
@ 2022-03-17 3:57 ` Bin Meng
2022-03-17 9:57 ` Frank Chang
2022-03-17 10:50 ` Frank Chang
2 siblings, 0 replies; 4+ messages in thread
From: Bin Meng @ 2022-03-17 3:57 UTC (permalink / raw)
To: Atish Patra
Cc: open list:RISC-V, Heiko Stubner, Anup Patel, Bin Meng,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Thu, Mar 17, 2022 at 1:58 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter ISA extensions as well.
>
> Generate the extended ISA string by appending the available ISA extensions
> to the "riscv,isa" string if it is enabled so that kernel can process it.
>
> [1] https://lkml.org/lkml/2022/2/15/263
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Suggested-by: Heiko Stubner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Changes from v5->v6:
> 1. Improved commit message.
> 2. Fixed a typo for Zfh.
>
> Changes from v4->v5:
> 1. Fixed the order of Zxx extensions.
> 2. Added a comment clearly describing the rules of extension order.
>
> Changes from v3->v4:
> 1. Fixed the order of the extension names.
> 2. Added all the available ISA extensions in Qemu.
>
> Changes from v2->v3:
> 1. Used g_strconcat to replace snprintf & a max isa string length as
> suggested by Anup.
> 2. I have not included the Tested-by Tag from Heiko because the
> implementation changed from v2 to v3.
>
> Changes from v1->v2:
> 1. Improved the code redability by using arrays instead of individual check
> ---
> target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddda4906ffb7..937ccdda997b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V CPU definitions */
>
> +struct isa_ext_data {
> + const char *name;
> + bool enabled;
> +};
> +
> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
> const char * const riscv_int_regnames[] = {
> @@ -898,6 +903,60 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
> +
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> +{
> + char *old = *isa_str;
> + char *new = *isa_str;
> + int i;
> +
> + /**
> + * Here are the ordering rules of extension naming defined by RISC-V
> + * specification :
> + * 1. All extensions should be separated from from other multi-letter
redundant "from"
> + * extensions by an underscore.
> + * 2. The first letter following the 'Z' conventionally indicates the most
> + * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
> + * If multiple 'Z' extensions are named, they should be ordered first
> + * by category, then alphabetically within a category.
> + * 3. Standard supervisor-level extensions (starts with 'S') should be
> + * listed after standard unprivileged extensions. If multiple
> + * supervisor-level extensions are listed, they should be ordered
> + * alphabetically.
> + * 4. Non-standard extensions (starts with 'X') must be listed after all
> + * standard extensions. They must be separated from other multi-letter
> + * extensions by an underscore.
> + */
> + struct isa_ext_data isa_edata_arr[] = {
> + ISA_EDATA_ENTRY(zfh, ext_zfh),
> + ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> + ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> + ISA_EDATA_ENTRY(zdinx, ext_zdinx),
> + ISA_EDATA_ENTRY(zba, ext_zba),
> + ISA_EDATA_ENTRY(zbb, ext_zbb),
> + ISA_EDATA_ENTRY(zbc, ext_zbc),
> + ISA_EDATA_ENTRY(zbs, ext_zbs),
> + ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> + ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> + ISA_EDATA_ENTRY(zhinx, ext_zhinx),
> + ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
> + ISA_EDATA_ENTRY(svinval, ext_svinval),
> + ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> + ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> + if (isa_edata_arr[i].enabled) {
> + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> + g_free(old);
> + old = new;
> + }
> + }
> +
> + *isa_str = new;
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> @@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> + riscv_isa_string_ext(cpu, &isa_str, maxlen);
> return isa_str;
> }
>
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v6] target/riscv: Add isa extenstion strings to the device tree
2022-03-16 17:57 [PATCH v6] target/riscv: Add isa extenstion strings to the device tree Atish Patra
2022-03-17 3:57 ` Bin Meng
@ 2022-03-17 9:57 ` Frank Chang
2022-03-17 10:50 ` Frank Chang
2 siblings, 0 replies; 4+ messages in thread
From: Frank Chang @ 2022-03-17 9:57 UTC (permalink / raw)
To: Atish Patra
Cc: open list:RISC-V, Heiko Stubner, Anup Patel, Bin Meng,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 4701 bytes --]
On Thu, Mar 17, 2022 at 1:58 AM Atish Patra <atishp@rivosinc.com> wrote:
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter ISA extensions as well.
>
> Generate the extended ISA string by appending the available ISA extensions
> to the "riscv,isa" string if it is enabled so that kernel can process it.
>
> [1] https://lkml.org/lkml/2022/2/15/263
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Suggested-by: Heiko Stubner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Changes from v5->v6:
> 1. Improved commit message.
> 2. Fixed a typo for Zfh.
>
> Changes from v4->v5:
> 1. Fixed the order of Zxx extensions.
> 2. Added a comment clearly describing the rules of extension order.
>
> Changes from v3->v4:
> 1. Fixed the order of the extension names.
> 2. Added all the available ISA extensions in Qemu.
>
> Changes from v2->v3:
> 1. Used g_strconcat to replace snprintf & a max isa string length as
> suggested by Anup.
> 2. I have not included the Tested-by Tag from Heiko because the
> implementation changed from v2 to v3.
>
> Changes from v1->v2:
> 1. Improved the code redability by using arrays instead of individual check
> ---
> target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddda4906ffb7..937ccdda997b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V CPU definitions */
>
> +struct isa_ext_data {
> + const char *name;
> + bool enabled;
> +};
> +
> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
> const char * const riscv_int_regnames[] = {
> @@ -898,6 +903,60 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
> +
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int
> max_str_len)
> +{
> + char *old = *isa_str;
> + char *new = *isa_str;
> + int i;
> +
> + /**
> + * Here are the ordering rules of extension naming defined by RISC-V
> + * specification :
> + * 1. All extensions should be separated from from other multi-letter
> + * extensions by an underscore.
> + * 2. The first letter following the 'Z' conventionally indicates the
> most
> + * closely related alphabetical extension category,
> IMAFDQLCBKJTPVH.
> + * If multiple 'Z' extensions are named, they should be ordered
> first
> + * by category, then alphabetically within a category.
> + * 3. Standard supervisor-level extensions (starts with 'S') should be
> + * listed after standard unprivileged extensions. If multiple
> + * supervisor-level extensions are listed, they should be ordered
> + * alphabetically.
> + * 4. Non-standard extensions (starts with 'X') must be listed after
> all
> + * standard extensions. They must be separated from other
> multi-letter
> + * extensions by an underscore.
> + */
> + struct isa_ext_data isa_edata_arr[] = {
> + ISA_EDATA_ENTRY(zfh, ext_zfh),
> + ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> + ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> + ISA_EDATA_ENTRY(zdinx, ext_zdinx),
> + ISA_EDATA_ENTRY(zba, ext_zba),
> + ISA_EDATA_ENTRY(zbb, ext_zbb),
> + ISA_EDATA_ENTRY(zbc, ext_zbc),
> + ISA_EDATA_ENTRY(zbs, ext_zbs),
> + ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> + ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> + ISA_EDATA_ENTRY(zhinx, ext_zhinx),
> + ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
> + ISA_EDATA_ENTRY(svinval, ext_svinval),
> + ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> + ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> + if (isa_edata_arr[i].enabled) {
> + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> + g_free(old);
> + old = new;
> + }
> + }
> +
> + *isa_str = new;
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> @@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> + riscv_isa_string_ext(cpu, &isa_str, maxlen);
> return isa_str;
> }
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v6] target/riscv: Add isa extenstion strings to the device tree
2022-03-16 17:57 [PATCH v6] target/riscv: Add isa extenstion strings to the device tree Atish Patra
2022-03-17 3:57 ` Bin Meng
2022-03-17 9:57 ` Frank Chang
@ 2022-03-17 10:50 ` Frank Chang
2 siblings, 0 replies; 4+ messages in thread
From: Frank Chang @ 2022-03-17 10:50 UTC (permalink / raw)
To: Atish Patra
Cc: open list:RISC-V, Heiko Stubner, Anup Patel, Bin Meng,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
[-- Attachment #1: Type: text/plain, Size: 4710 bytes --]
On Thu, Mar 17, 2022 at 1:58 AM Atish Patra <atishp@rivosinc.com> wrote:
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter ISA extensions as well.
>
> Generate the extended ISA string by appending the available ISA extensions
> to the "riscv,isa" string if it is enabled so that kernel can process it.
>
> [1] https://lkml.org/lkml/2022/2/15/263
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Suggested-by: Heiko Stubner <heiko@sntech.de>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Changes from v5->v6:
> 1. Improved commit message.
> 2. Fixed a typo for Zfh.
>
> Changes from v4->v5:
> 1. Fixed the order of Zxx extensions.
> 2. Added a comment clearly describing the rules of extension order.
>
> Changes from v3->v4:
> 1. Fixed the order of the extension names.
> 2. Added all the available ISA extensions in Qemu.
>
> Changes from v2->v3:
> 1. Used g_strconcat to replace snprintf & a max isa string length as
> suggested by Anup.
> 2. I have not included the Tested-by Tag from Heiko because the
> implementation changed from v2 to v3.
>
> Changes from v1->v2:
> 1. Improved the code redability by using arrays instead of individual check
> ---
> target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddda4906ffb7..937ccdda997b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V CPU definitions */
>
> +struct isa_ext_data {
> + const char *name;
> + bool enabled;
>
Nit: Should be 4 spaces indent.
Regards,
Frank Chang
> +};
> +
> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
> const char * const riscv_int_regnames[] = {
> @@ -898,6 +903,60 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> +#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
> +
> +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int
> max_str_len)
> +{
> + char *old = *isa_str;
> + char *new = *isa_str;
> + int i;
> +
> + /**
> + * Here are the ordering rules of extension naming defined by RISC-V
> + * specification :
> + * 1. All extensions should be separated from from other multi-letter
> + * extensions by an underscore.
> + * 2. The first letter following the 'Z' conventionally indicates the
> most
> + * closely related alphabetical extension category,
> IMAFDQLCBKJTPVH.
> + * If multiple 'Z' extensions are named, they should be ordered
> first
> + * by category, then alphabetically within a category.
> + * 3. Standard supervisor-level extensions (starts with 'S') should be
> + * listed after standard unprivileged extensions. If multiple
> + * supervisor-level extensions are listed, they should be ordered
> + * alphabetically.
> + * 4. Non-standard extensions (starts with 'X') must be listed after
> all
> + * standard extensions. They must be separated from other
> multi-letter
> + * extensions by an underscore.
> + */
> + struct isa_ext_data isa_edata_arr[] = {
> + ISA_EDATA_ENTRY(zfh, ext_zfh),
> + ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> + ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> + ISA_EDATA_ENTRY(zdinx, ext_zdinx),
> + ISA_EDATA_ENTRY(zba, ext_zba),
> + ISA_EDATA_ENTRY(zbb, ext_zbb),
> + ISA_EDATA_ENTRY(zbc, ext_zbc),
> + ISA_EDATA_ENTRY(zbs, ext_zbs),
> + ISA_EDATA_ENTRY(zve32f, ext_zve32f),
> + ISA_EDATA_ENTRY(zve64f, ext_zve64f),
> + ISA_EDATA_ENTRY(zhinx, ext_zhinx),
> + ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
> + ISA_EDATA_ENTRY(svinval, ext_svinval),
> + ISA_EDATA_ENTRY(svnapot, ext_svnapot),
> + ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> + if (isa_edata_arr[i].enabled) {
> + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> + g_free(old);
> + old = new;
> + }
> + }
> +
> + *isa_str = new;
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> @@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> + riscv_isa_string_ext(cpu, &isa_str, maxlen);
> return isa_str;
> }
>
> --
> 2.25.1
>
>
>
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^ permalink raw reply [flat|nested] 4+ messages in thread