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Date: Tue, 19 Aug 2014 15:21:35 -0300
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From: Martin Galvan <martin.galvan@tallertechnologies.com>
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Subject: Re: [Qemu-devel] [PATCH] target-arm: Fix resetting issues on
	ARMv7-M CPUs
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On Tue, Aug 19, 2014 at 11:16 AM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> On 19 August 2014 14:25, Martin Galvan
> <martin.galvan@tallertechnologies.com> wrote:
>> On Tue, Aug 19, 2014 at 10:06 AM, Peter Maydell
>> <peter.maydell@linaro.org> wrote:
>>> I'm afraid this looks like the wrong fix for the problem you're seeing.
>>> The bug you need to fix is that the ROM contents got zeroed.
>>> The reset code is correct to reload SP and PC from memory --
>>> this is what the hardware does.
>>
>> Indeed, but aren't the ROM contents supposed to get zeroed? Otherwise,
>> why would we call cpu_flish_icache_range? I'm afraid "fixing" that may
>> have some unwanted side effects.
>
> Why do you think cpu_flush_icache_range has anything to do
> with this? All that does is ensure that the host's instruction
> cache has no stale contents for the ROM region. It doesn't
> zero anything. (It's mostly there for the benefit of KVM, not TCG.)
>

Indeed, I missed the g_free just above the call to
cpu_flush_icache_range in rom_reset. Is there any particular reason
why we're doing that g_free?