[Qemu-devel] Enable floating point support in qemu-system-aarch64

[Qemu-devel] Enable floating point support in qemu-system-aarch64

[Semion Prihodko]

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Hi guys,

Please explain me how to enable floating point and SIMD support in
qemu-system-aarch64 (ver.2.1.0). My code is booting and working correctly
before calling variadic function (with empty body), and then crashes. Here
is the code of the problematic function:

   0: d102c3ff sub sp, sp, #0xb0
   4: f90043e2 str x2, [sp,#128]
   8: f90047e3 str x3, [sp,#136]
   c: f9004be4 str x4, [sp,#144]
  10: f9004fe5 str x5, [sp,#152]
  14: f90053e6 str x6, [sp,#160]
  18: f90057e7 str x7, [sp,#168]
  1c: 3d8003e0 str q0, [sp]
  20: 3d8007e1 str q1, [sp,#16]
  24: 3d800be2 str q2, [sp,#32]
  28: 3d800fe3 str q3, [sp,#48]
  2c: 3d8013e4 str q4, [sp,#64]
  30: 3d8017e5 str q5, [sp,#80]
  34: 3d801be6 str q6, [sp,#96]
  38: 3d801fe7 str q7, [sp,#112]
  3c: 52800000 mov w0, #0x0                   // #0
  40: 9102c3ff add sp, sp, #0xb0
  44: d65f03c0 ret

 You can see the callee is saving GP and FP registers to stack which is OK.
Then I replaced the call with the following instruction:

str q0, [sp]

The same crash. Does it mean that I should enable floating point support?
How can I do it? In register dump (using instruction msr FPEXC32_EL2, x1) I
can see that FPEXC32_EL2 EN bit is set. What's a problem here? Thanks.

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