From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:55585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RnuTP-0008Ak-9k for qemu-devel@nongnu.org; Thu, 19 Jan 2012 11:04:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RnuQV-0000XT-Ie for qemu-devel@nongnu.org; Thu, 19 Jan 2012 11:01:33 -0500 Received: from mail-vx0-f173.google.com ([209.85.220.173]:46408) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RnuQV-0000XN-DU for qemu-devel@nongnu.org; Thu, 19 Jan 2012 11:01:23 -0500 Received: by vcbfo14 with SMTP id fo14so69353vcb.4 for ; Thu, 19 Jan 2012 08:01:22 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <20120116084122.GB2729@stefanha-thinkpad.localdomain> <20120117010434.GA52852@cs.nctu.edu.tw> From: Rajat Goyal Date: Thu, 19 Jan 2012 16:00:41 +0000 Message-ID: Content-Type: multipart/alternative; boundary=f46d042f9118f1f25404b6e3ac44 Subject: Re: [Qemu-devel] Get only TCG code without execution List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org --f46d042f9118f1f25404b6e3ac44 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Thank you so much for your help Peter. I was using version 0.15.1. On 1.0, it works like a dream! I was not talking about semantics of individual instructions but semantics of the whole multi-threaded program. Multi-threaded programs can lead to several different (most of which are unintended) states of the CPU. What states are possible is described in a mathematically rigorous definition of the ARM memory model. My task is to implement this memory model over TCG ops and then compare the results on several different (multi-threaded) litmus tests with the implementation of the memory model over ARM instructions. For the same task, I need QEMU to give me the TCG translation for code which it never branches into and hence, never needs to translate and execute (because ARM multiprocessors can perform speculative execution)= . Rajat. On Tue, Jan 17, 2012 at 8:33 AM, Peter Maydell wr= ote: > On 17 January 2012 01:04, =E9=99=B3=E9=9F=8B=E4=BB=BB wrote: > >> > What is the way out of this? The reason I need TCG code is because m= y > >> > project work is to write a semantics for TCG micro-operations and th= en > >> > compare my semantics with a semantics for ARM instructions being > written by > >> > someone else. To test my semantics, I need the corresponding TCG cod= e > for > >> > several different multi-threaded ARM binaries. > >> > >> Why does this have to be a multi-threaded binary? In the multithreaded > >> case, the instructions executed by QEMU won't be deterministic (it wil= l > >> depend on how the host OS schedules the multiple threads) so it's goin= g > >> to be hard to compare a long trace output to something else. > > > > I guess Rajat's goal is to compare the "semantics" of TCG ops and ARM > binary, > > therefore the non-deterministic might not be the issue. Or he want to u= se > > "semantics" to solve the non-deterministic problem. > > But if you're looking at the semantics at a level where you don't > care about the non-determinism of the threading, you might just > as well look at them at an individual instruction or TB level, > in which case a single threaded program is just as good and less > confusing, surely? > > -- PMM > --=20 Rajat Goyal 5th year undergraduate student Integrated Master of Technology Mathematics and Computing Department of Mathematics IIT Delhi --f46d042f9118f1f25404b6e3ac44 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Thank you so much for your help Peter. I was using version 0.15.1. On 1.0, = it works like a dream!

I was not talking about semantics of individu= al instructions but semantics of the whole multi-threaded program. Multi-th= readed programs can lead to several different (most of which are unintended= ) states of the CPU. What states are possible is described in a mathematica= lly rigorous definition of the ARM memory model. My task is to implement th= is memory model over TCG ops and then compare the results on several differ= ent (multi-threaded) litmus tests with the implementation of the memory mod= el over ARM instructions. For the same task, I need QEMU to give me the TCG= translation for code which it never branches into and hence, never needs t= o translate and execute (because ARM multiprocessors can perform speculativ= e execution).

Rajat.

On Tue, Jan 17, 2012 at 8:33 A= M, Peter Maydell <peter.maydell@linaro.org> wrote:
On 17 January 2012 01:04, =E9=99=B3=E9=9F=8B=E4=BB=BB <chenwj@iis.sinica.edu.tw<= /a>> wrote:
>> > What is the way out of this? The reason I need TCG code is be= cause my
>> > project work is to write a semantics for TCG micro-operations= and then
>> > compare my semantics with a semantics for ARM instructions be= ing written by
>> > someone else. To test my semantics, I need the corresponding = TCG code for
>> > several different multi-threaded ARM binaries.
>>
>> Why does this have to be a multi-threaded binary? In the multithre= aded
>> case, the instructions executed by QEMU won't be deterministic= (it will
>> depend on how the host OS schedules the multiple threads) so it= 9;s going
>> to be hard to compare a long trace output to something else.
>
> =C2=A0I guess Rajat's goal is to compare the "semantics"= of TCG ops and ARM binary,
> therefore the non-deterministic might not be the issue. Or he want to = use
> "semantics" to solve the non-deterministic problem.

But if you're looking at the semantics at a level where you don&#= 39;t
care about the non-determinism of the threading, you might just
as well look at them at an individual instruction or TB level,
in which case a single threaded program is just as good and less
confusing, surely?

-- PMM



--
Rajat Goyal
5th year= undergraduate student
Integrated Master of Technology
Mathematics an= d Computing
Department of Mathematics
IIT Delhi
--f46d042f9118f1f25404b6e3ac44--