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X-Received-From: 2607:f8b0:4864:20::d41 X-Mailman-Approved-At: Tue, 28 Jan 2020 23:52:43 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Nicholas Piggin , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Jan 29, 2020 at 2:09 PM David Gibson wrote: > > On Mon, Jan 27, 2020 at 03:45:05PM +0100, C=C3=A9dric Le Goater wrote: > > From: Benjamin Herrenschmidt > > *snip* > > + > > +/* > > + * The CONFIG_DATA register expects little endian accesses, but as the > > + * region is big endian, we have to swap the value. > > + */ > > +static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off, > > + unsigned size, uint64_t val) > > +{ > > + uint32_t cfg_addr, limit; > > + PCIDevice *pdev; > > + > > + pdev =3D pnv_phb4_find_cfg_dev(phb); > > + if (!pdev) { > > + return; > > + } > > + cfg_addr =3D (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; > > + cfg_addr |=3D off; > > + limit =3D pci_config_size(pdev); > > + if (limit <=3D cfg_addr) { > > + /* > > + * conventional pci device can be behind pcie-to-pci bridge. > > + * 256 <=3D addr < 4K has no effects. > > + */ > > + return; > > + } > > + switch (size) { > > + case 1: > > + break; > > + case 2: > > + val =3D bswap16(val); > > I'm a little confused by these byteswaps. As I see below the device > is set to big endian, so the values passed in here should already be > in host-native endian. Why do you need the swap? Are some of the > registers in the bank BE and some LE? All the registers are BE except for CONFIG_DATA, which isn't actually a register. It's really a window into the config space of the device specified in CONFIG_ADDR so it doesn't do any byte-swapping. > > + break; > > + case 4: > > + val =3D bswap32(val); > > + break; > > + default: > > + g_assert_not_reached(); > > + } > > + pci_host_config_write_common(pdev, cfg_addr, limit, val, size); > > +}