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boundary="0000000000000f462105f5656880" Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=vilen.kamalov@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --0000000000000f462105f5656880 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable nevermind, I do not understand how it is fixing the problem. :) On Fri, Feb 24, 2023 at 1:13=E2=80=AFAM Vilen Kamalov wrote: > Yes, agree that my explanation is incorrect, just looked again, there is = a > code in the default, down the line 5488 > > default: > /* Otherwise, generate EFLAGS and replace the C bit. */ > gen_compute_eflags(s); > tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, > * s->tmp4,* ctz32(CC_C), 1); > break; > > and changing tmp0 to tmp4 fixes the issue. > > On Fri, Feb 24, 2023 at 1:01=E2=80=AFAM Richard Henderson < > richard.henderson@linaro.org> wrote: > >> On 2/23/23 11:13, ~vilenka wrote: >> > From: Vilen Kamalov >> > >> > gen_shift_rm_T1 in the uses wrong tmp0 register, eflags calculation >> uses tmp4 at target/i386/tcg/translate.c, line 5488 >> > `tcg_gen_mov_tl(cpu_cc_src, s->tmp4);` >> >> The line you quote only applies to the bit instructions, bt/bts/btr/btc, >> so your >> explanation is clearly incorrect. >> >> > push rcx >> > mov dword ptr [rsp], 010000000h >> > mov rcx, 01eh >> > sar dword ptr [rsp], cl >> > jnc pass1 >> > int 3 >> > pass1: >> > mov dword ptr [rsp], 0ffffffffh >> > mov rcx, 01eh >> > sar dword ptr [rsp], cl >> > jc pass2 >> > int 3 >> > pass2: >> > pop rcx >> >> Thanks for the test case. >> >> > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c >> > index 9d9392b009..9048e22868 100644 >> > --- a/target/i386/tcg/translate.c >> > +++ b/target/i386/tcg/translate.c >> > @@ -1686,27 +1686,27 @@ static void gen_shift_rm_T1(DisasContext *s, >> MemOp ot, int op1, >> > } >> > >> > tcg_gen_andi_tl(s->T1, s->T1, mask); >> > - tcg_gen_subi_tl(s->tmp0, s->T1, 1); >> > + tcg_gen_subi_tl(s->tmp4, s->T1, 1); >> > >> > if (is_right) { >> > if (is_arith) { >> > gen_exts(ot, s->T0); >> > - tcg_gen_sar_tl(s->tmp0, s->T0, s->tmp0); >> > + tcg_gen_sar_tl(s->tmp4, s->T0, s->tmp4); >> > tcg_gen_sar_tl(s->T0, s->T0, s->T1); >> > } else { >> > gen_extu(ot, s->T0); >> > - tcg_gen_shr_tl(s->tmp0, s->T0, s->tmp0); >> > + tcg_gen_shr_tl(s->tmp4, s->T0, s->tmp4); >> > tcg_gen_shr_tl(s->T0, s->T0, s->T1); >> > } >> > } else { >> > - tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0); >> > + tcg_gen_shl_tl(s->tmp4, s->T0, s->tmp4); >> > tcg_gen_shl_tl(s->T0, s->T0, s->T1); >> > } >> > >> > /* store */ >> > gen_op_st_rm_T0_A0(s, ot, op1); >> > >> > - gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, is_right); >> > + gen_shift_flags(s, ot, s->T0, s->tmp4, s->T1, is_right); >> > } >> >> The use of tmp0 vs tmp4 is completely local to this function. >> Within gen_shift_flags, the 4th argument is consistently used, and >> neither tmp0 nor tmp4 >> are referenced. >> >> If this does fix the issue, that means there's some other explanation, >> and possibly some >> deeper fix is required. >> >> >> r~ >> > --0000000000000f462105f5656880 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
nevermind, I do not understand how it is fixing the proble= m. :)

On Fri, Feb 24, 2023 at 1:13=E2=80=AFAM Vilen Kamalov <vilen.kamalov@gmail.com> wrote:
Yes,= agree that my explanation is incorrect, just looked again, there is a code= in the default, down the line 5488

=C2=A0 =C2=A0 = =C2=A0 =C2=A0 default:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Othe= rwise, generate EFLAGS and replace the C bit. =C2=A0*/
=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 gen_compute_eflags(s);
=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, s->tmp4,=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ctz32(CC_C), 1);
=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;

a= nd changing tmp0 to tmp4 fixes the issue.

On Fri, Feb 24, 2023 at 1:01= =E2=80=AFAM Richard Henderson <richard.henderson@linaro.org> wrote:
On 2/23/23 11:13, ~vil= enka wrote:
> From: Vilen Kamalov <vilen.kamalov@gmail.com>
>
> gen_shift_rm_T1 in the uses wrong tmp0 register, eflags calculation us= es tmp4 at target/i386/tcg/translate.c, line 5488
> `tcg_gen_mov_tl(cpu_cc_src, s->tmp4);`

The line you quote only applies to the bit instructions, bt/bts/btr/btc, so= your
explanation is clearly incorrect.

> push rcx
> mov dword ptr [rsp], 010000000h
> mov rcx, 01eh
> sar dword ptr [rsp], cl
> jnc pass1
> int 3
> pass1:
> mov dword ptr [rsp], 0ffffffffh
> mov rcx, 01eh
> sar dword ptr [rsp], cl
> jc pass2
> int 3
> pass2:
> pop rcx

Thanks for the test case.

> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c=
> index 9d9392b009..9048e22868 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -1686,27 +1686,27 @@ static void gen_shift_rm_T1(DisasContext *s, M= emOp ot, int op1,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_andi_tl(s->T1, s->T1, mask); > -=C2=A0 =C2=A0 tcg_gen_subi_tl(s->tmp0, s->T1, 1);
> +=C2=A0 =C2=A0 tcg_gen_subi_tl(s->tmp4, s->T1, 1);
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0if (is_right) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (is_arith) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_exts(ot, s-&= gt;T0);
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_sar_tl(s->tmp0, = s->T0, s->tmp0);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_sar_tl(s->tmp4, = s->T0, s->tmp4);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_sar_tl(s= ->T0, s->T0, s->T1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_extu(ot, s-&= gt;T0);
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shr_tl(s->tmp0, = s->T0, s->tmp0);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shr_tl(s->tmp4, = s->T0, s->tmp4);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_shr_tl(s= ->T0, s->T0, s->T1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shl_tl(s->tmp0, s->T0, s-&g= t;tmp0);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shl_tl(s->tmp4, s->T0, s-&g= t;tmp4);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_shl_tl(s->T0, s->= ;T0, s->T1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* store */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0gen_op_st_rm_T0_A0(s, ot, op1);
>=C2=A0 =C2=A0
> -=C2=A0 =C2=A0 gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, = is_right);
> +=C2=A0 =C2=A0 gen_shift_flags(s, ot, s->T0, s->tmp4, s->T1, = is_right);
>=C2=A0 =C2=A0}

The use of tmp0 vs tmp4 is completely local to this function.
Within gen_shift_flags, the 4th argument is consistently used, and neither = tmp0 nor tmp4
are referenced.

If this does fix the issue, that means there's some other explanation, = and possibly some
deeper fix is required.


r~
--0000000000000f462105f5656880--