From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70CCAC61DA4 for ; Thu, 23 Feb 2023 22:14:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pVJqK-0000kD-41; Thu, 23 Feb 2023 17:13:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pVJqH-0000iS-Ji for qemu-devel@nongnu.org; Thu, 23 Feb 2023 17:13:33 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pVJqF-0005iO-Py for qemu-devel@nongnu.org; Thu, 23 Feb 2023 17:13:33 -0500 Received: by mail-ed1-x536.google.com with SMTP id da10so48957568edb.3 for ; Thu, 23 Feb 2023 14:13:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677190410; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=dNuFY5ZM1LXdYMwKJZhJq9DSmINOrQiB5j7nGjId/Ho=; b=M9v050K32BxA1lHW+7X0FKn8Kq3RwFtUTSIhAe95LjptV3EayNf3q3LIX0me7JPvSv r8DcTYiP3XEcxBER09oOOUpUXfrCWM6/yrFm621m9e9Lu0Ihvwmc1esC0Z7lHOD0uPXe Jgf5SdZHsADluywnvbSizzJ4mJCjCvcgCrZ/VHllbQD10ndTwfGAanvku9dB8lydDnrM X0SDkLWRewnVGPgX4prmNKehrwraUAV6bqB4DMI01aJc7Ne/ZaeZpSMgkHQ5Wq7DiNKG LOl6Jxy+5jyNqqUTx5qJXi6CJSEPtzUz7QUUUy8DjdEMO7G4Qbfc16Kmn9++PPjNm8z8 QsMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677190410; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dNuFY5ZM1LXdYMwKJZhJq9DSmINOrQiB5j7nGjId/Ho=; b=7rJdk9Jb71WO5U7pEXXXY0xzTZQk4NyAb3KV6uW93r2er8CiIbRwZ3ms4g6bfAWAFZ RtmvQWDVXkv8uAb8wOXLGl9Ip+1DFQUqZn10ch3CGcgipn+5Sz4Uqo1f+CsL7Z5rrBx2 fMQ0FMtFtrHU0tdRTo/jLOvidq22yHkrjBiKl+hq8K/RkbytnBwpyGHMIsESPJFmGwqU WQt3d0wLHewLn/c9Ael4RRwtFAb/hUKdsedyoKgbMq21oVbHzjnOyWwG6BhV9Jn49HfH gmRcysusr89GEiQrqGo/LaMwm48HS7OmcOux0AEFnLEky5sxXdtpBxHx8BH0byexcr5/ OVuQ== X-Gm-Message-State: AO0yUKW5W1RLcxU6+h1oysStTmcEiVvrn9TVc3Alpwm/puSPbkeniDVD X4tqO0CrgVQotAOn/JfdUdelodqZwFnMj7EHLMI= X-Google-Smtp-Source: AK7set88k6JvMEXd+u7EKDrSmiQqQ9LTWdDT1dzCtAOG74ArggmUhHfuqFUHFVqPgg8S+VyXIv/mDpmmoAEgdtQHwZk= X-Received: by 2002:a50:d086:0:b0:4ad:72b2:cf57 with SMTP id v6-20020a50d086000000b004ad72b2cf57mr6286657edd.0.1677190409583; Thu, 23 Feb 2023 14:13:29 -0800 (PST) MIME-Version: 1.0 References: <167718710208.23058.11278141733696221981-1@git.sr.ht> <1ecf3d94-8e0e-94fd-51a0-7772ea8cb786@linaro.org> In-Reply-To: <1ecf3d94-8e0e-94fd-51a0-7772ea8cb786@linaro.org> From: Vilen Kamalov Date: Fri, 24 Feb 2023 01:13:18 +0300 Message-ID: Subject: Re: [PATCH qemu 1/1] target/i386: Fix gen_shift_rm_T1, wrong eflags calculation To: Richard Henderson Cc: qemu-devel@nongnu.org, philmd@linaro.org, pbonzini@redhat.com Content-Type: multipart/alternative; boundary="00000000000095838c05f5655278" Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=vilen.kamalov@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --00000000000095838c05f5655278 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Yes, agree that my explanation is incorrect, just looked again, there is a code in the default, down the line 5488 default: /* Otherwise, generate EFLAGS and replace the C bit. */ gen_compute_eflags(s); tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, * s->tmp4,* ctz32(CC_C), 1); break; and changing tmp0 to tmp4 fixes the issue. On Fri, Feb 24, 2023 at 1:01=E2=80=AFAM Richard Henderson < richard.henderson@linaro.org> wrote: > On 2/23/23 11:13, ~vilenka wrote: > > From: Vilen Kamalov > > > > gen_shift_rm_T1 in the uses wrong tmp0 register, eflags calculation use= s > tmp4 at target/i386/tcg/translate.c, line 5488 > > `tcg_gen_mov_tl(cpu_cc_src, s->tmp4);` > > The line you quote only applies to the bit instructions, bt/bts/btr/btc, > so your > explanation is clearly incorrect. > > > push rcx > > mov dword ptr [rsp], 010000000h > > mov rcx, 01eh > > sar dword ptr [rsp], cl > > jnc pass1 > > int 3 > > pass1: > > mov dword ptr [rsp], 0ffffffffh > > mov rcx, 01eh > > sar dword ptr [rsp], cl > > jc pass2 > > int 3 > > pass2: > > pop rcx > > Thanks for the test case. > > > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c > > index 9d9392b009..9048e22868 100644 > > --- a/target/i386/tcg/translate.c > > +++ b/target/i386/tcg/translate.c > > @@ -1686,27 +1686,27 @@ static void gen_shift_rm_T1(DisasContext *s, > MemOp ot, int op1, > > } > > > > tcg_gen_andi_tl(s->T1, s->T1, mask); > > - tcg_gen_subi_tl(s->tmp0, s->T1, 1); > > + tcg_gen_subi_tl(s->tmp4, s->T1, 1); > > > > if (is_right) { > > if (is_arith) { > > gen_exts(ot, s->T0); > > - tcg_gen_sar_tl(s->tmp0, s->T0, s->tmp0); > > + tcg_gen_sar_tl(s->tmp4, s->T0, s->tmp4); > > tcg_gen_sar_tl(s->T0, s->T0, s->T1); > > } else { > > gen_extu(ot, s->T0); > > - tcg_gen_shr_tl(s->tmp0, s->T0, s->tmp0); > > + tcg_gen_shr_tl(s->tmp4, s->T0, s->tmp4); > > tcg_gen_shr_tl(s->T0, s->T0, s->T1); > > } > > } else { > > - tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0); > > + tcg_gen_shl_tl(s->tmp4, s->T0, s->tmp4); > > tcg_gen_shl_tl(s->T0, s->T0, s->T1); > > } > > > > /* store */ > > gen_op_st_rm_T0_A0(s, ot, op1); > > > > - gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, is_right); > > + gen_shift_flags(s, ot, s->T0, s->tmp4, s->T1, is_right); > > } > > The use of tmp0 vs tmp4 is completely local to this function. > Within gen_shift_flags, the 4th argument is consistently used, and neithe= r > tmp0 nor tmp4 > are referenced. > > If this does fix the issue, that means there's some other explanation, an= d > possibly some > deeper fix is required. > > > r~ > --00000000000095838c05f5655278 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Yes, agree that my explanation is incorrect, just looked a= gain, there is a code in the default, down the line 5488

=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 /* Otherwise, generate EFLAGS and replace the C bit. =C2=A0*/=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 gen_compute_eflags(s);
=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_deposit_tl(cpu_cc_src, cpu_c= c_src, s->tmp4,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ctz32(CC_= C), 1);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
=

and changing tmp0 to tmp4 fixes the issue.
<= br>
On Fri,= Feb 24, 2023 at 1:01=E2=80=AFAM Richard Henderson <richard.henderson@linaro.org> wrote:
=
On 2/23/23 11:13, ~= vilenka wrote:
> From: Vilen Kamalov <vilen.kamalov@gmail.com>
>
> gen_shift_rm_T1 in the uses wrong tmp0 register, eflags calculation us= es tmp4 at target/i386/tcg/translate.c, line 5488
> `tcg_gen_mov_tl(cpu_cc_src, s->tmp4);`

The line you quote only applies to the bit instructions, bt/bts/btr/btc, so= your
explanation is clearly incorrect.

> push rcx
> mov dword ptr [rsp], 010000000h
> mov rcx, 01eh
> sar dword ptr [rsp], cl
> jnc pass1
> int 3
> pass1:
> mov dword ptr [rsp], 0ffffffffh
> mov rcx, 01eh
> sar dword ptr [rsp], cl
> jc pass2
> int 3
> pass2:
> pop rcx

Thanks for the test case.

> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c=
> index 9d9392b009..9048e22868 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -1686,27 +1686,27 @@ static void gen_shift_rm_T1(DisasContext *s, M= emOp ot, int op1,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_andi_tl(s->T1, s->T1, mask); > -=C2=A0 =C2=A0 tcg_gen_subi_tl(s->tmp0, s->T1, 1);
> +=C2=A0 =C2=A0 tcg_gen_subi_tl(s->tmp4, s->T1, 1);
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0if (is_right) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (is_arith) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_exts(ot, s-&= gt;T0);
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_sar_tl(s->tmp0, = s->T0, s->tmp0);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_sar_tl(s->tmp4, = s->T0, s->tmp4);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_sar_tl(s= ->T0, s->T0, s->T1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_extu(ot, s-&= gt;T0);
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shr_tl(s->tmp0, = s->T0, s->tmp0);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shr_tl(s->tmp4, = s->T0, s->tmp4);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_shr_tl(s= ->T0, s->T0, s->T1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shl_tl(s->tmp0, s->T0, s-&g= t;tmp0);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_shl_tl(s->tmp4, s->T0, s-&g= t;tmp4);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_gen_shl_tl(s->T0, s->= ;T0, s->T1);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* store */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0gen_op_st_rm_T0_A0(s, ot, op1);
>=C2=A0 =C2=A0
> -=C2=A0 =C2=A0 gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, = is_right);
> +=C2=A0 =C2=A0 gen_shift_flags(s, ot, s->T0, s->tmp4, s->T1, = is_right);
>=C2=A0 =C2=A0}

The use of tmp0 vs tmp4 is completely local to this function.
Within gen_shift_flags, the 4th argument is consistently used, and neither = tmp0 nor tmp4
are referenced.

If this does fix the issue, that means there's some other explanation, = and possibly some
deeper fix is required.


r~
--00000000000095838c05f5655278--