From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wuouv-0000Zk-Dk for qemu-devel@nongnu.org; Wed, 11 Jun 2014 16:14:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wuoup-0003PZ-BO for qemu-devel@nongnu.org; Wed, 11 Jun 2014 16:14:41 -0400 Received: from mail-qa0-f53.google.com ([209.85.216.53]:54675) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wuoup-0003PO-5t for qemu-devel@nongnu.org; Wed, 11 Jun 2014 16:14:35 -0400 Received: by mail-qa0-f53.google.com with SMTP id j15so375403qaq.26 for ; Wed, 11 Jun 2014 13:14:34 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1402326269-8573-15-git-send-email-edgar.iglesias@gmail.com> References: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> <1402326269-8573-15-git-send-email-edgar.iglesias@gmail.com> Date: Wed, 11 Jun 2014 15:14:34 -0500 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=001a11c139bac61b3104fb951741 Subject: Re: [Qemu-devel] [PATCH v2 14/17] target-arm: A64: Emulate the HVC insn List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: Peter Maydell , Peter Crosthwaite , Rob Herring , Fabian Aggeler , QEMU Developers , Alexander Graf , Blue Swirl , John Williams , pbonzini@redhat.com, =?UTF-8?B?QWxleCBCZW5uw6ll?= , Christoffer Dall , rth@twiddle.net --001a11c139bac61b3104fb951741 Content-Type: text/plain; charset=UTF-8 On 9 June 2014 10:04, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 1 + > target-arm/helper-a64.c | 1 + > target-arm/helper.c | 28 +++++++++++++++++++++++++++- > target-arm/helper.h | 1 + > target-arm/internals.h | 6 ++++++ > target-arm/op_helper.c | 21 +++++++++++++++++++++ > target-arm/translate-a64.c | 21 ++++++++++++++++----- > 7 files changed, 73 insertions(+), 6 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 6aed57c..679f85f 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -51,6 +51,7 @@ > #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ > #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ > #define EXCP_STREX 10 > +#define EXCP_HVC 11 /* HyperVisor Call */ > > #define ARMV7M_EXCP_RESET 1 > #define ARMV7M_EXCP_NMI 2 > diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c > index c91005f..974fa66 100644 > --- a/target-arm/helper-a64.c > +++ b/target-arm/helper-a64.c > @@ -475,6 +475,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) > case EXCP_BKPT: > case EXCP_UDEF: > case EXCP_SWI: > + case EXCP_HVC: > env->cp15.esr_el[new_el] = env->exception.syndrome; > break; > case EXCP_IRQ: > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 86e098f..89ccfa8 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3282,7 +3282,33 @@ void switch_mode(CPUARMState *env, int mode) > */ > unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) > { > - return 1; > + CPUARMState *env = cs->env_ptr; > + unsigned int cur_el = arm_current_pl(env); > + unsigned int target_el = 1; > + bool route_to_el2 = false; > + /* FIXME: Use actual secure state. */ > + bool secure = false; > + > + if (!env->aarch64) { > + /* TODO: Add EL2 and 3 exception handling for AArch32. */ > + return 1; > + } > + > + if (!secure > + && arm_feature(env, ARM_FEATURE_EL2) > + && cur_el < 2 > + && (env->cp15.hcr_el2 & HCR_TGE)) { > + route_to_el2 = true; > + } > + > + target_el = MAX(cur_el, route_to_el2 ? 2 : 1); > + > + switch (excp_idx) { > + case EXCP_HVC: > + target_el = MAX(target_el, 2); > + break; > + } > + return target_el; > } > > static void v7m_push(CPUARMState *env, uint32_t val) > diff --git a/target-arm/helper.h b/target-arm/helper.h > index b63fd0f..fb711be 100644 > --- a/target-arm/helper.h > +++ b/target-arm/helper.h > @@ -50,6 +50,7 @@ DEF_HELPER_2(exception_internal, void, env, i32) > DEF_HELPER_3(exception_with_syndrome, void, env, i32, i32) > DEF_HELPER_1(wfi, void, env) > DEF_HELPER_1(wfe, void, env) > +DEF_HELPER_2(hvc, void, env, i32) > > DEF_HELPER_3(cpsr_write, void, env, i32, i32) > DEF_HELPER_1(cpsr_read, i32, env) > diff --git a/target-arm/internals.h b/target-arm/internals.h > index 707643e..2da7a1b 100644 > --- a/target-arm/internals.h > +++ b/target-arm/internals.h > @@ -53,6 +53,7 @@ static const char * const excnames[] = { > [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", > [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", > [EXCP_STREX] = "QEMU intercept of STREX", > + [EXCP_HVC] = "Hypervisor Call", > }; > > static inline void arm_log_exception(int idx) > @@ -204,6 +205,11 @@ static inline uint32_t syn_aa64_svc(uint16_t imm16) > return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | imm16; > } > > +static inline uint32_t syn_aa64_hvc(uint16_t imm16) > +{ > + return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | imm16; > +} > + > See comment on 13/17 with regards to uint16_t. > static inline uint32_t syn_aa32_svc(uint16_t imm16, bool is_thumb) > { > return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | imm16 > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 25ad902..e51cbd6 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -369,6 +369,27 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t > op, uint32_t imm) > } > } > > +void HELPER(hvc)(CPUARMState *env, uint32_t syndrome) > +{ > + bool udef; > + > + /* We've already checked that EL2 exists at translation time. > + * EL3.HCE has priority over EL2.HCD. > + */ > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + udef = !(env->cp15.scr_el3 & SCR_HCE); > HVC is also undefined if we are in secure state, do we trap this elsewhere? > + } else { > + udef = env->cp15.hcr_el2 & HCR_HCD; > + } > + > + if (udef) { > + env->exception.syndrome = syn_uncategorized(); > + raise_exception(env, EXCP_UDEF); > + } > + env->exception.syndrome = syndrome; > + raise_exception(env, EXCP_HVC); > +} > + > void HELPER(exception_return)(CPUARMState *env) > { > int cur_el = arm_current_pl(env); > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index 3589898..0319061 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -1434,17 +1434,28 @@ static void disas_exc(DisasContext *s, uint32_t > insn) > int opc = extract32(insn, 21, 3); > int op2_ll = extract32(insn, 0, 5); > uint16_t imm16 = extract32(insn, 5, 16); > + TCGv_i32 tmp; > > switch (opc) { > case 0: > - /* SVC, HVC, SMC; since we don't support the Virtualization > - * or TrustZone extensions these all UNDEF except SVC. > - */ > - if (op2_ll != 1) { > + switch (op2_ll) { > + case 1: > + gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16)); > + break; > + case 2: > + if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_pl == > 0) { > + unallocated_encoding(s); > + break; > + } > + tmp = tcg_const_i32(syn_aa64_hvc(imm16)); > + gen_a64_set_pc_im(s->pc); > + gen_helper_hvc(cpu_env, tmp); > + tcg_temp_free_i32(tmp); > + break; > + default: > unallocated_encoding(s); > break; > } > - gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16)); > break; > case 1: > if (op2_ll != 0) { > -- > 1.8.3.2 > > --001a11c139bac61b3104fb951741 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable



On 9 June 2014 10:04, Edgar E. Iglesias <edgar.iglesias@gma= il.com> wrote:
From: "Edgar E. Iglesias" <edgar.iglesias@x= ilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
=C2=A0target-arm/cpu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A01 +
=C2=A0target-arm/helper-a64.c =C2=A0 =C2=A0| =C2=A01 +
=C2=A0target-arm/helper.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| 28 +++++++++++++++++= ++++++++++-
=C2=A0target-arm/helper.h =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A01 +
=C2=A0target-arm/internals.h =C2=A0 =C2=A0 | =C2=A06 ++++++
=C2=A0target-arm/op_helper.c =C2=A0 =C2=A0 | 21 +++++++++++++++++++++
=C2=A0target-arm/translate-a64.c | 21 ++++++++++++++++-----
=C2=A07 files changed, 73 insertions(+), 6 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6aed57c..679f85f 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -51,6 +51,7 @@
=C2=A0#define EXCP_EXCEPTION_EXIT =C2=A08 =C2=A0 /* Return from v7M excepti= on. =C2=A0*/
=C2=A0#define EXCP_KERNEL_TRAP =C2=A0 =C2=A0 9 =C2=A0 /* Jumped to kernel c= ode page. =C2=A0*/
=C2=A0#define EXCP_STREX =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A010
+#define EXCP_HVC =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A011 =C2=A0 /* Hyp= erVisor Call */

=C2=A0#define ARMV7M_EXCP_RESET =C2=A0 1
=C2=A0#define ARMV7M_EXCP_NMI =C2=A0 =C2=A0 2
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index c91005f..974fa66 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -475,6 +475,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0case EXCP_BKPT:
=C2=A0 =C2=A0 =C2=A0case EXCP_UDEF:
=C2=A0 =C2=A0 =C2=A0case EXCP_SWI:
+ =C2=A0 =C2=A0case EXCP_HVC:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cp15.esr_el[new_el] =3D env->e= xception.syndrome;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0case EXCP_IRQ:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 86e098f..89ccfa8 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3282,7 +3282,33 @@ void switch_mode(CPUARMState *env, int mode)
=C2=A0 */
=C2=A0unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)<= br> =C2=A0{
- =C2=A0 =C2=A0return 1;
+ =C2=A0 =C2=A0CPUARMState *env =3D cs->env_ptr;
+ =C2=A0 =C2=A0unsigned int cur_el =3D arm_current_pl(env);
+ =C2=A0 =C2=A0unsigned int target_el =3D 1;
+ =C2=A0 =C2=A0bool route_to_el2 =3D false;
+ =C2=A0 =C2=A0/* FIXME: Use actual secure state. =C2=A0*/
+ =C2=A0 =C2=A0bool secure =3D false;
+
+ =C2=A0 =C2=A0if (!env->aarch64) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/* TODO: Add EL2 and 3 exception handling for = AArch32. =C2=A0*/
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0return 1;
+ =C2=A0 =C2=A0}
+
+ =C2=A0 =C2=A0if (!secure
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0&& arm_feature(env, ARM_FEATURE_EL2) + =C2=A0 =C2=A0 =C2=A0 =C2=A0&& cur_el < 2
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0&& (env->cp15.hcr_el2 & HCR_TGE= )) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0route_to_el2 =3D true;
+ =C2=A0 =C2=A0}
+
+ =C2=A0 =C2=A0target_el =3D MAX(cur_el, route_to_el2 ? 2 : 1);
+
+ =C2=A0 =C2=A0switch (excp_idx) {
+ =C2=A0 =C2=A0case EXCP_HVC:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0target_el =3D MAX(target_el, 2);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0return target_el;
=C2=A0}

=C2=A0static void v7m_push(CPUARMState *env, uint32_t val)
diff --git a/target-arm/helper.h b/target-arm/helper.h
index b63fd0f..fb711be 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -50,6 +50,7 @@ DEF_HELPER_2(exception_internal, void, env, i32)
=C2=A0DEF_HELPER_3(exception_with_syndrome, void, env, i32, i32)
=C2=A0DEF_HELPER_1(wfi, void, env)
=C2=A0DEF_HELPER_1(wfe, void, env)
+DEF_HELPER_2(hvc, void, env, i32)

=C2=A0DEF_HELPER_3(cpsr_write, void, env, i32, i32)
=C2=A0DEF_HELPER_1(cpsr_read, i32, env)
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 707643e..2da7a1b 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -53,6 +53,7 @@ static const char * const excnames[] =3D {
=C2=A0 =C2=A0 =C2=A0[EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit= ",
=C2=A0 =C2=A0 =C2=A0[EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel c= ommpage",
=C2=A0 =C2=A0 =C2=A0[EXCP_STREX] =3D "QEMU intercept of STREX", + =C2=A0 =C2=A0[EXCP_HVC] =3D "Hypervisor Call",
=C2=A0};

=C2=A0static inline void arm_log_exception(int idx)
@@ -204,6 +205,11 @@ static inline uint32_t syn_aa64_svc(uint16_t imm16) =C2=A0 =C2=A0 =C2=A0return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_= IL | imm16;
=C2=A0}

+static inline uint32_t syn_aa64_hvc(uint16_t imm16)
+{
+ =C2=A0 =C2=A0return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | = imm16;
+}
+

See comment on 13/17 with regards to = uint16_t.
=C2=A0
=C2=A0static inline uint32_t syn_aa32_svc(uint16_t imm16, bool is_thumb) =C2=A0{
=C2=A0 =C2=A0 =C2=A0return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | imm16 diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 25ad902..e51cbd6 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -369,6 +369,27 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t o= p, uint32_t imm)
=C2=A0 =C2=A0 =C2=A0}
=C2=A0}

+void HELPER(hvc)(CPUARMState *env, uint32_t syndrome)
+{
+ =C2=A0 =C2=A0bool udef;
+
+ =C2=A0 =C2=A0/* We've already checked that EL2 exists at translation = time.
+ =C2=A0 =C2=A0 * EL3.HCE has priority over EL2.HCD.
+ =C2=A0 =C2=A0 */
+ =C2=A0 =C2=A0if (arm_feature(env, ARM_FEATURE_EL3)) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0udef =3D !(env->cp15.scr_el3 & SCR_HCE)= ;

HVC is also undefined if we are in se= cure state, do we trap this elsewhere?
=C2=A0
+ =C2=A0 =C2=A0} else {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0udef =3D env->cp15.hcr_el2 & HCR_HCD; + =C2=A0 =C2=A0}
+
+ =C2=A0 =C2=A0if (udef) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0env->exception.syndrome =3D syn_uncategoriz= ed();
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0raise_exception(env, EXCP_UDEF);
+ =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0env->exception.syndrome =3D syndrome;
+ =C2=A0 =C2=A0raise_exception(env, EXCP_HVC);
+}
+
=C2=A0void HELPER(exception_return)(CPUARMState *env)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0int cur_el =3D arm_current_pl(env);
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 3589898..0319061 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1434,17 +1434,28 @@ static void disas_exc(DisasContext *s, uint32_t ins= n)
=C2=A0 =C2=A0 =C2=A0int opc =3D extract32(insn, 21, 3);
=C2=A0 =C2=A0 =C2=A0int op2_ll =3D extract32(insn, 0, 5);
=C2=A0 =C2=A0 =C2=A0uint16_t imm16 =3D extract32(insn, 5, 16);
+ =C2=A0 =C2=A0TCGv_i32 tmp;

=C2=A0 =C2=A0 =C2=A0switch (opc) {
=C2=A0 =C2=A0 =C2=A0case 0:
- =C2=A0 =C2=A0 =C2=A0 =C2=A0/* SVC, HVC, SMC; since we don't support t= he Virtualization
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 * or TrustZone extensions these all UNDEF exc= ept SVC.
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 */
- =C2=A0 =C2=A0 =C2=A0 =C2=A0if (op2_ll !=3D 1) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0switch (op2_ll) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0case 1:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_exception_insn(s, 0, EXCP_SW= I, syn_aa64_svc(imm16));
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0case 2:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!arm_dc_feature(s, ARM_FEATU= RE_EL2) || s->current_pl =3D=3D 0) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unallocated_encodi= ng(s);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tmp =3D tcg_const_i32(syn_aa64_h= vc(imm16));
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_a64_set_pc_im(s->pc);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_helper_hvc(cpu_env, tmp); + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_temp_free_i32(tmp);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0default:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unallocated_encoding(s); =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
- =C2=A0 =C2=A0 =C2=A0 =C2=A0gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_sv= c(imm16));
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0case 1:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (op2_ll !=3D 0) {
--
1.8.3.2


--001a11c139bac61b3104fb951741--