From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49242) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHZr0-0005Av-97 for qemu-devel@nongnu.org; Wed, 13 Aug 2014 10:48:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHZqv-0008WP-3I for qemu-devel@nongnu.org; Wed, 13 Aug 2014 10:48:42 -0400 Received: from mail-ig0-f182.google.com ([209.85.213.182]:48546) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHZqu-0008WH-SN for qemu-devel@nongnu.org; Wed, 13 Aug 2014 10:48:37 -0400 Received: by mail-ig0-f182.google.com with SMTP id c1so1939712igq.3 for ; Wed, 13 Aug 2014 07:48:35 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20140804151901.GB27221@zapo.iiNet> References: <1402994746-8328-1-git-send-email-edgar.iglesias@gmail.com> <1402994746-8328-9-git-send-email-edgar.iglesias@gmail.com> <20140804151901.GB27221@zapo.iiNet> Date: Wed, 13 Aug 2014 09:48:35 -0500 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=089e0149c57efa3bf2050083e12a Subject: Re: [Qemu-devel] [PATCH v3 08/16] target-arm: Add SCR_EL3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: Peter Maydell , Peter Crosthwaite , Rob Herring , Fabian Aggeler , QEMU Developers , Alexander Graf , Blue Swirl , John Williams , Paolo Bonzini , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Christoffer Dall , Richard Henderson --089e0149c57efa3bf2050083e12a Content-Type: text/plain; charset=UTF-8 Hi Edgar, I was just writing a test to verify the correct behavior of the SCR AW/FW bits and I think there is an issue. During an SCR write an initial valid mask is set from SCR_MASK which is defined to not include these bits. Then these bits are hard-coded into the write value using RES1. Last, the new value is masked against the valid bits for which these bits are masked off. I have a number of questions: - Why are we marking these bits off as reserved? Shouldn't they be RW? - Are you intending to always enable them or always disable them? - Why are we attempting to hard-code them 'on' in the value? Is it because they have no value when VIRT is enabled? If so, we should check for EL2. Thanks for any insight. Greg On 4 August 2014 10:19, Edgar E. Iglesias wrote: > On Fri, Aug 01, 2014 at 02:34:14PM +0100, Peter Maydell wrote: > > On 17 June 2014 09:45, Edgar E. Iglesias > wrote: > > > From: "Edgar E. Iglesias" > > > > > > Signed-off-by: Edgar E. Iglesias > > > --- > > > target-arm/cpu.h | 16 +++++++++++++++- > > > target-arm/helper.c | 31 ++++++++++++++++++++++++++++++- > > > 2 files changed, 45 insertions(+), 2 deletions(-) > > > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > > index fd57fb5..fa8dee0 100644 > > > --- a/target-arm/cpu.h > > > +++ b/target-arm/cpu.h > > > @@ -172,7 +172,6 @@ typedef struct CPUARMState { > > > uint64_t c1_sys; /* System control register. */ > > > uint64_t c1_coproc; /* Coprocessor access register. */ > > > uint32_t c1_xscaleauxcr; /* XScale auxiliary control > register. */ > > > - uint32_t c1_scr; /* secure config register. */ > > > uint64_t ttbr0_el1; /* MMU translation table base 0. */ > > > uint64_t ttbr1_el1; /* MMU translation table base 1. */ > > > uint64_t c2_control; /* MMU translation table base control. > */ > > > @@ -185,6 +184,7 @@ typedef struct CPUARMState { > > > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access > permissions */ > > > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access > permissions */ > > > uint64_t hcr_el2; /* Hypervisor configuration register */ > > > + uint32_t scr_el3; /* Secure configuration register. */ > > > uint32_t ifsr_el2; /* Fault status registers. */ > > > uint64_t esr_el[4]; > > > uint32_t c6_region[8]; /* MPU base/size registers. */ > > > @@ -562,6 +562,20 @@ static inline void xpsr_write(CPUARMState *env, > uint32_t val, uint32_t mask) > > > #define HCR_ID (1ULL << 33) > > > #define HCR_MASK ((1ULL << 34) - 1) > > > > > > +#define SCR_NS (1U << 0) > > > +#define SCR_IRQ (1U << 1) > > > +#define SCR_FIQ (1U << 2) > > > +#define SCR_EA (1U << 3) > > > +#define SCR_SMD (1U << 7) > > > +#define SCR_HCE (1U << 8) > > > +#define SCR_SIF (1U << 9) > > > +#define SCR_RW (1U << 10) > > > +#define SCR_ST (1U << 11) > > > +#define SCR_TWI (1U << 12) > > > +#define SCR_TWE (1U << 13) > > > +#define SCR_RES1_MASK (3U << 4) > > > +#define SCR_MASK (0x3fff & ~SCR_RES1_MASK) > > > + > > > /* Return the current FPSCR value. */ > > > uint32_t vfp_get_fpscr(CPUARMState *env); > > > void vfp_set_fpscr(CPUARMState *env, uint32_t val); > > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > > index b04fb5d..6bacc24 100644 > > > --- a/target-arm/helper.c > > > +++ b/target-arm/helper.c > > > @@ -793,7 +793,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > > > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > > > .resetvalue = 0 }, > > > { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = > 0, > > > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, > cp15.c1_scr), > > > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, > cp15.scr_el3), > > > .resetvalue = 0, }, > > > > It's awkward that this is now separate from the AArch64 reginfo > > below, because it makes it non-obvious that they're both the > > same underlying state. In particular that probably means this > > one now needs a NO_MIGRATE marker? > > Yes, I've moved this into the el3 structure and added NO_MIGRATE. > > Thanks, > Edgar > > > > > > > { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, > > > .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, > > > @@ -2161,6 +2161,31 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = > { > > > REGINFO_SENTINEL > > > }; > > > > > > +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > > > +{ > > > + uint32_t valid_mask = SCR_MASK; > > > + > > > + if (!arm_feature(env, ARM_FEATURE_EL2)) { > > > + valid_mask &= ~SCR_HCE; > > > + > > > + /* On ARMv7, SMD (or SCD as it is called in v7) is only > > > + * supported if EL2 exists. The bit is UNK/SBZP when > > > + * EL2 is unavailable. In QEMU ARMv7, we force it to always > zero > > > + * when EL2 is unavailable. > > > + */ > > > + if (arm_feature(env, ARM_FEATURE_V7)) { > > > + valid_mask &= ~SCR_SMD; > > > + } > > > + } > > > + > > > + /* Set RES1 bits. */ > > > + value |= SCR_RES1_MASK; > > > + > > > + /* Clear RES0 bits. */ > > > + value &= valid_mask; > > > + raw_write(env, ri, value); > > > +} > > > + > > > static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > > > { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, > > > .type = ARM_CP_NO_MIGRATE, > > > @@ -2183,6 +2208,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = > { > > > .access = PL3_RW, .writefn = vbar_write, > > > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), > > > .resetvalue = 0 }, > > > + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, > > > + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, > > > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, > cp15.scr_el3), > > > + .writefn = scr_write }, > > > REGINFO_SENTINEL > > > }; > > > > thanks > > -- PMM > --089e0149c57efa3bf2050083e12a Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Hi Edgar,

I was just writing a te= st to verify the correct behavior of the SCR AW/FW bits and I think there i= s an issue.

During an SCR write an initial valid mask is= set from SCR_MASK which is defined to not include these bits. =C2=A0Then t= hese bits are hard-coded into the write value using RES1. =C2=A0Last, the n= ew value is masked against the valid bits for which these bits are masked o= ff.

I have a number of questions:
- Why are we ma= rking these bits off as reserved? =C2=A0Shouldn't they be RW?
- Are you intending to always enable them or always disable them?
- Why are we attempting to hard-code them 'on' in the value? =C2=A0= Is it because they have no value when VIRT is enabled? =C2=A0If so, we shou= ld check for EL2.

Thanks for any insight.

Greg


On 4 August 2014 10:19, Edgar E. Iglesias &= lt;edgar.igle= sias@gmail.com> wrote:
On F= ri, Aug 01, 2014 at 02:34:14PM +0100, Peter Maydell wrote:
> On 17 June 2014 09:45, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > =C2=A0target-arm/cpu.h =C2=A0 =C2=A0| 16 +++++++++++++++-
> > =C2=A0target-arm/helper.c | 31 ++++++++++++++++++++++++++++++- > > =C2=A02 files changed, 45 insertions(+), 2 deletions(-)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index fd57fb5..fa8dee0 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -172,7 +172,6 @@ typedef struct CPUARMState {
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t c1_sys; /* System cont= rol register. =C2=A0*/
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t c1_coproc; /* Coproces= sor access register. =C2=A0*/
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t c1_xscaleauxcr; /* XSc= ale auxiliary control register. =C2=A0*/
> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t c1_scr; /* secure config re= gister. =C2=A0*/
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t ttbr0_el1; /* MMU tran= slation table base 0. */
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t ttbr1_el1; /* MMU tran= slation table base 1. */
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t c2_control; /* MMU tra= nslation table base control. =C2=A0*/
> > @@ -185,6 +184,7 @@ typedef struct CPUARMState {
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t pmsav5_data_ap; /* PMS= Av5 MPU data access permissions */
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t pmsav5_insn_ap; /* PMS= Av5 MPU insn access permissions */
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t hcr_el2; /* Hypervisor= configuration register */
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t scr_el3; /* Secure configur= ation register. =C2=A0*/
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t ifsr_el2; /* Fault sta= tus registers. =C2=A0*/
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t esr_el[4];
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t c6_region[8]; /* MPU b= ase/size registers. =C2=A0*/
> > @@ -562,6 +562,20 @@ static inline void xpsr_write(CPUARMState *e= nv, uint32_t val, uint32_t mask)
> > =C2=A0#define HCR_ID =C2=A0 =C2=A0 =C2=A0 =C2=A0(1ULL << 33= )
> > =C2=A0#define HCR_MASK =C2=A0 =C2=A0 =C2=A0((1ULL << 34) - = 1)
> >
> > +#define SCR_NS =C2=A0 =C2=A0 =C2=A0 =C2=A0(1U << 0)
> > +#define SCR_IRQ =C2=A0 =C2=A0 =C2=A0 (1U << 1)
> > +#define SCR_FIQ =C2=A0 =C2=A0 =C2=A0 (1U << 2)
> > +#define SCR_EA =C2=A0 =C2=A0 =C2=A0 =C2=A0(1U << 3)
> > +#define SCR_SMD =C2=A0 =C2=A0 =C2=A0 (1U << 7)
> > +#define SCR_HCE =C2=A0 =C2=A0 =C2=A0 (1U << 8)
> > +#define SCR_SIF =C2=A0 =C2=A0 =C2=A0 (1U << 9)
> > +#define SCR_RW =C2=A0 =C2=A0 =C2=A0 =C2=A0(1U << 10)
> > +#define SCR_ST =C2=A0 =C2=A0 =C2=A0 =C2=A0(1U << 11)
> > +#define SCR_TWI =C2=A0 =C2=A0 =C2=A0 (1U << 12)
> > +#define SCR_TWE =C2=A0 =C2=A0 =C2=A0 (1U << 13)
> > +#define SCR_RES1_MASK (3U << 4)
> > +#define SCR_MASK =C2=A0 =C2=A0 =C2=A0(0x3fff & ~SCR_RES1_MAS= K)
> > +
> > =C2=A0/* Return the current FPSCR value. =C2=A0*/
> > =C2=A0uint32_t vfp_get_fpscr(CPUARMState *env);
> > =C2=A0void vfp_set_fpscr(CPUARMState *env, uint32_t val);
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index b04fb5d..6bacc24 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -793,7 +793,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D= {
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState,= cp15.vbar_el[1]),
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },
> > =C2=A0 =C2=A0 =C2=A0{ .name =3D "SCR", .cp =3D 15, .crn= =3D 1, .crm =3D 1, .opc1 =3D 0, .opc2 =3D 0,
> > - =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .fieldoffset =3D offset= of(CPUARMState, cp15.c1_scr),
> > + =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .fieldoffset =3D offset= of(CPUARMState, cp15.scr_el3),
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0, },
>
> It's awkward that this is now separate from the AArch64 reginfo > below, because it makes it non-obvious that they're both the
> same underlying state. In particular that probably means this
> one now needs a NO_MIGRATE marker?

Yes, I've moved this into the el3 structure and added NO_MI= GRATE.

Thanks,
Edgar


>
> > =C2=A0 =C2=A0 =C2=A0{ .name =3D "CCSIDR", .state =3D AR= M_CP_STATE_BOTH,
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .crn =3D 0, .crm =3D 0, .= opc1 =3D 1, .opc2 =3D 0,
> > @@ -2161,6 +2161,31 @@ static const ARMCPRegInfo v8_el2_cp_reginf= o[] =3D {
> > =C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL
> > =C2=A0};
> >
> > +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, = uint64_t value)
> > +{
> > + =C2=A0 =C2=A0uint32_t valid_mask =3D SCR_MASK;
> > +
> > + =C2=A0 =C2=A0if (!arm_feature(env, ARM_FEATURE_EL2)) {
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0valid_mask &=3D ~SCR_HCE;
> > +
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0/* On ARMv7, SMD (or SCD as it is ca= lled in v7) is only
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 * supported if EL2 exists. The bit = is UNK/SBZP when
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 * EL2 is unavailable. In QEMU ARMv7= , we force it to always zero
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 * when EL2 is unavailable.
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 */
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (arm_feature(env, ARM_FEATURE_V7)= ) {
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0valid_mask &=3D ~S= CR_SMD;
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> > + =C2=A0 =C2=A0}
> > +
> > + =C2=A0 =C2=A0/* Set RES1 bits. =C2=A0*/
> > + =C2=A0 =C2=A0value |=3D SCR_RES1_MASK;
> > +
> > + =C2=A0 =C2=A0/* Clear RES0 bits. =C2=A0*/
> > + =C2=A0 =C2=A0value &=3D valid_mask;
> > + =C2=A0 =C2=A0raw_write(env, ri, value);
> > +}
> > +
> > =C2=A0static const ARMCPRegInfo v8_el3_cp_reginfo[] =3D {
> > =C2=A0 =C2=A0 =C2=A0{ .name =3D "ELR_EL3", .state =3D A= RM_CP_STATE_AA64,
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.type =3D ARM_CP_NO_MIGRATE,
> > @@ -2183,6 +2208,10 @@ static const ARMCPRegInfo v8_el3_cp_reginf= o[] =3D {
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .writefn =3D vbar_= write,
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState,= cp15.vbar_el[3]),
> > =C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },
> > + =C2=A0 =C2=A0{ .name =3D "SCR_EL3", .state =3D ARM_CP= _STATE_AA64,
> > + =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm = =3D 1, .opc2 =3D 0,
> > + =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offset= of(CPUARMState, cp15.scr_el3),
> > + =C2=A0 =C2=A0 =C2=A0.writefn =3D scr_write },
> > =C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL
> > =C2=A0};
>
> thanks
> -- PMM

--089e0149c57efa3bf2050083e12a--