From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMeM-0002Lk-DO for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:46:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlMeH-00088e-Uw for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:46:46 -0500 Received: from mail-qa0-f47.google.com ([209.85.216.47]:53653) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMeH-00088a-Pz for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:46:41 -0500 Received: by mail-qa0-f47.google.com with SMTP id dc16so8688001qab.6 for ; Mon, 03 Nov 2014 10:46:39 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <2195206.F4HeItVKYs@dabox> References: <1533701.HoIoT00ynE@dabox> <2195206.F4HeItVKYs@dabox> Date: Mon, 3 Nov 2014 12:46:39 -0600 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=001a11c3ec7a56c26e0506f8c4f5 Subject: Re: [Qemu-devel] State of ARM FIQ in Qemu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tim Sander Cc: QEMU Developers --001a11c3ec7a56c26e0506f8c4f5 Content-Type: text/plain; charset=UTF-8 On 3 November 2014 10:22, Tim Sander wrote: > Hi Greg > > Thanks for your fast reply. > > I am still in the process of getting the security extension portion of > the > > GIC patches fully up and running. By the sounds of your use, it sounds > > like you just want FIQ support not necessarily secure GIC support. Would > > this be correct? > Yes. More elaborate i am working on a modified cortexa9 versatile express, > where i added my virtual test hardware. > > > I recently sent out an updated set of patches for review that contain GIC > > interrupt grouping and FIQ enablement along with secure extension > > infrastructure. If interested, you can find the patches here: > > > > http://lists.nongnu.org/archive/html/qemu-devel/2014-10/msg03921.html > > > > Alternatively, it sounds like you have access to the Linaro GIT repos, in > > which case you can use the following repo/branch that contains the same > > patches. It is based on fairly recent upstream bits. > > > > repo: git://git.linaro.org/people/greg.bellows/qemu.git > > branch: tzqemu_gic_v2 > > > > If you don't need the security extensions, then you shouldn't need to do > > anything to the code to get FIQ support on vexpress-a9/15 or virt > machines. > Ok but i think i see a RAZ codepath in qemu when accessing the gic > registers > configuring the interrupt group. > > Please let me know if you have any further questions or issues. > I have the problem that the secure_extn property is not set and i have not > figured out a way to set these. The corresponding code is a slighly > modified > vexpress_common_init in hw/arm/vexpress.c.:519. > > I guess setting the property would be done by > qdev_prop_set_bool(dev,"security_extn",TRUE); > but i fail to find the "dev" from the GIC i could use as argument. > > Attached is also a snipped from a debugger run verifing that its indeed > s->security-extn which is missing. > > Ah... Yes, using A9 (GICv1) which means you don't have grouping without the security extensions. I tried enabling the security extensions and things hung, however, I was able to boot A9 Linux and use FIQs with the following change: diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c09358c..813ae92 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -29,6 +29,8 @@ static void a9mp_priv_initfn(Object *obj) object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); This may be at least a workaround for you while I figure out where the security configuration gets hung-up. Can you give this a try and see if you can make progress? The security extensions aspect of the code is fairly untested as I still need secure address space support, so there may be glitches when security is enabled. Best regards > Tim > > Breakpoint 3, gic_dist_writeb (opaque=0x555556368a80, offset=136, value=0) > at > hw/intc/arm_gic.c:820 > 820 } else if (offset >= 0x80) { > (gdb) list > 815 s->enabled = (value & 0x1); > 816 DPRINTF("Distribution %sabled\n", s->enabled ? > "En" : > "Dis"); > 817 } > 818 } else if (offset < 4) { > 819 /* ignored. */ > 820 } else if (offset >= 0x80) { > 821 /* Interrupt Group Registers > 822 * > 823 * For GIC with Security Extn and Non-secure access > RAZ/WI > 824 * For GICv1 without Security Extn RAZ/WI > (gdb) n > 826 if (!(s->security_extn && ns_access()) && > (gdb) n > 828 || s->revision == 2)) { > (gdb) n > 999 gic_update(s); > (gdb) print s->security_extn > $2 = false > > --001a11c3ec7a56c26e0506f8c4f5 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On 3 November 2014 10:22, Tim Sander <tim@krieglstein.org> wrote:
Hi Greg

Thanks for your fast reply.
> I am still in the process of getting the sec= urity extension portion of the
> GIC patches fully up and running.=C2=A0 By the sounds of your use, it = sounds
> like you just want FIQ support not necessarily secure GIC support.=C2= =A0 Would
> this be correct?
Yes. More elaborate i am working on a modified co= rtexa9 versatile express,
where i added my virtual test hardware.

> I recently sent out an updated set of patche= s for review that contain GIC
> interrupt grouping and FIQ enablement along with secure extension
> infrastructure.=C2=A0 If interested, you can find the patches here: >
> http://lists.nongnu.org/archive/html/qemu-dev= el/2014-10/msg03921.html
>
> Alternatively, it sounds like you have access to the Linaro GIT repos,= in
> which case you can use the following repo/branch that contains the sam= e
> patches.=C2=A0 It is based on fairly recent upstream bits.
>
> repo: git://git.linaro.org/people/greg.bellows/qemu.git
> branch: tzqemu_gic_v2
>
> If you don't need the security extensions, then you shouldn't = need to do
> anything to the code to get FIQ support on vexpress-a9/15 or virt mach= ines.
Ok but i think i see a RAZ codepath in qemu when = accessing the gic registers
configuring the interrupt group.=C2=A0
=
> Please let me know if you have any further q= uestions or issues.
I have the problem that the secure= _extn property is not set and i have not
figured out a way to set these.=C2=A0 The corresponding code is a slighly m= odified
vexpress_common_init in hw/arm/vexpress.c.:519.

I guess setting the property would be done by
qdev_prop_set_bool(dev,"security_extn",TRUE);
but i fail to find the "dev" from the GIC i could use as argument= .

Attached is also a snipped from a debugger run verifing that its indeed
s->security-extn which is missing.


Ah... Yes, using A9 (GICv1= ) which means you don't have grouping without the security extensions.= =C2=A0 I tried enabling the security extensions and things hung, however, I= was able to boot A9 Linux and use FIQs with the following change:

=C2=A0diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index c09358c..813ae92 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -29,6 +29,8 @@ static void a9m= p_priv_initfn(Object *obj)
=C2=A0
=C2=A0 =C2=A0 =C2=A0o= bject_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
=C2=A0 =C2=A0 =C2=A0qdev_set_parent_bus(DEVICE(&s->gic), sysbus_ge= t_default());
+ =C2=A0 =C2=A0qdev_prop_set_uint32(DEVICE(&s-&= gt;gic), "revision", 2);
=C2=A0
=C2=A0 =C2=A0= =C2=A0object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_G= TIMER);
=C2=A0 =C2=A0 =C2=A0qdev_set_parent_bus(DEVICE(&s->= ;gtimer), sysbus_get_default());

=C2=A0
This may be at least a workaround for you while I figure out= where the security configuration gets hung-up.=C2=A0 Can you give this a t= ry and see if you can make progress?

The security = extensions aspect of the code is fairly untested as I still need secure add= ress space support, so there may be glitches when security is enabled.

Best regards
Tim

Breakpoint 3, gic_dist_writeb (opaque=3D0x555556368a80, offset=3D136, value= =3D0) at
hw/intc/arm_gic.c:820
820=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if (offset >= =3D 0x80) {
(gdb) list
815=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0s->enabled =3D (value & 0x1);
816=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0DPRINTF("Distribution %sabled\n", s->enabled ? "En&= quot; :
"Dis");
817=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
818=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if (offset < 4= ) {
819=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* ignored= .=C2=A0 */
820=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if (offset >= =3D 0x80) {
821=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Interru= pt Group Registers
822=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *
823=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * For GIC= with Security Extn and Non-secure access RAZ/WI
824=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * For GIC= v1 without Security Extn RAZ/WI
(gdb) n
826=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!(s-&g= t;security_extn && ns_access()) &&
(gdb) n
828=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|| s->revision =3D=3D 2)= ) {
(gdb) n
999=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gic_update(s);
(gdb) print s->security_extn
$2 =3D false


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