From: Greg Bellows <greg.bellows@linaro.org>
To: Sergey Fedorov <serge.fdrv@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
Date: Wed, 22 Apr 2015 09:04:25 -0500 [thread overview]
Message-ID: <CAOgzsHX1gemcWdVGdpE50+A+D19MLdvX_u-o3needeW21Ppe1g@mail.gmail.com> (raw)
In-Reply-To: <1429669112-29835-1-git-send-email-serge.fdrv@gmail.com>
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On Tue, Apr 21, 2015 at 9:18 PM, Sergey Fedorov <serge.fdrv@gmail.com>
wrote:
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> target-arm/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 986f04c..327b1e5 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
> unset_feature(env, ARM_FEATURE_EL3);
>
> /* Disable the security extension feature bits in the processor
> feature
> - * register as well. This is id_pfr1[7:4].
> + * registers as well. These are id_pfr1[7:4] and
> id_aa64pfr0[15:12].
> */
> cpu->id_pfr1 &= ~0xf0;
> + cpu->id_aa64pfr0 &= ~0xf000;
> }
>
> register_cp_regs_for_features(cpu);
> --
> 2.3.4
>
>
> Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
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next prev parent reply other threads:[~2015-04-22 14:04 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-22 2:18 [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled Sergey Fedorov
2015-04-22 14:04 ` Greg Bellows [this message]
2015-04-23 12:25 ` Peter Maydell
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