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From: Greg Bellows <greg.bellows@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH 1/2] target-arm: Split NO_MIGRATE into
 ALIAS and NO_RAW
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>, Christoffer Dall <christoffer.dall@linaro.org>, patches@linaro.org

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On 9 December 2014 at 13:46, Peter Maydell <peter.maydell@linaro.org> wrote:

> We currently mark ARM coprocessor/system register definitions with
> the flag ARM_CP_NO_MIGRATE for two different reasons:
> 1) register is an alias on to state that's also visible via
>    some other register, and that other register is the one
>    responsible for migrating the state
> 2) register is not actually state at all (for instance the TLB
>    or cache maintenance operation "registers") and it makes no
>    sense to attempt to migrate it or otherwise access the raw state
>
> This works fine for identifying which registers should be ignored
> when performing migration, but we also use the same functions for
> synchronizing system register state between QEMU and the kernel
> when using KVM. In this case we don't want to try to sync state
> into registers in category 2, but we do want to sync into registers
> in category 1, because the kernel might have picked a different
> one of the aliases as its choice for which one to expose for
> migration. (In particular, on 32 bit hosts the kernel will
> expose the state in the AArch32 version of the register, but
> TCG's convention is to mark the AArch64 version as the version
> to migrate, even if the CPU being emulated happens to be 32 bit,
> so almost all system registers will hit this issue now that we've
> added AArch64 system emulation.)
>
> Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW)
> corresponding to the two different reasons we might not want to
> migrate a register. When setting up the TCG list of registers to
> migrate we honour both flags; when populating the list from KVM,
> only ignore registers which are NO_RAW.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/cpu.h    |  15 +++-
>  target-arm/helper.c | 206
> ++++++++++++++++++++++++++--------------------------
>  2 files changed, 115 insertions(+), 106 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 7ba55f0..831a841 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1112,8 +1112,14 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t
> cpregid)
>   * a register definition to override a previous definition for the
>   * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
>   * old must have the OVERRIDE bit set.
> - * NO_MIGRATE indicates that this register should be ignored for
> migration;
> - * (eg because any state is accessed via some other coprocessor register).
> + * ALIAS indicates that this register is an alias view of some underlying
> + * state which is also visible via another register, and that the other
> + * register is handling migration; registers marked ALIAS will not be
> migrated
> + * but may have their state set by syncing of register state from KVM.
> + * NO_RAW indicates that this register has no underlying state and does
> not
> + * support raw access for state saving/loading; it will not be used for
> either
> + * migration or KVM state synchronization. (Typically this is for
> "registers"
> + * which are actually used as instructions for cache maintenance and so
> on.)
>   * IO indicates that this register does I/O and therefore its accesses
>   * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
>   * registers which implement clocks or timers require this.
> @@ -1123,8 +1129,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t
> cpregid)
>  #define ARM_CP_64BIT 4
>  #define ARM_CP_SUPPRESS_TB_END 8
>  #define ARM_CP_OVERRIDE 16
> -#define ARM_CP_NO_MIGRATE 32
> +#define ARM_CP_ALIAS 32
>  #define ARM_CP_IO 64
> +#define ARM_CP_NO_RAW 128
>  #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
>  #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
>  #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
> @@ -1134,7 +1141,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t
> cpregid)
>  /* Used only as a terminator for ARMCPRegInfo lists */
>  #define ARM_CP_SENTINEL 0xffff
>  /* Mask of only the flag bits in a type field */
> -#define ARM_CP_FLAG_MASK 0x7f
> +#define ARM_CP_FLAG_MASK 0xff
>
>  /* Valid values for ARMCPRegInfo state field, indicating which of
>   * the AArch32 and AArch64 execution states this register is visible in.
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 96abbed..d1b856c 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -189,7 +189,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
>              ok = false;
>              continue;
>          }
> -        if (ri->type & ARM_CP_NO_MIGRATE) {
> +        if (ri->type & ARM_CP_NO_RAW) {
>              continue;
>          }
>          cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
> @@ -212,7 +212,7 @@ bool write_list_to_cpustate(ARMCPU *cpu)
>              ok = false;
>              continue;
>          }
> -        if (ri->type & ARM_CP_NO_MIGRATE) {
> +        if (ri->type & ARM_CP_NO_RAW) {
>              continue;
>          }
>          /* Write value and confirm it reads back as written
> @@ -236,7 +236,7 @@ static void add_cpreg_to_list(gpointer key, gpointer
> opaque)
>      regidx = *(uint32_t *)key;
>      ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
>
> -    if (!(ri->type & ARM_CP_NO_MIGRATE)) {
> +    if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
>          cpu->cpreg_indexes[cpu->cpreg_array_len] =
> cpreg_to_kvm_id(regidx);
>          /* The value array need not be initialized at this point */
>          cpu->cpreg_array_len++;
> @@ -252,7 +252,7 @@ static void count_cpreg(gpointer key, gpointer opaque)
>      regidx = *(uint32_t *)key;
>      ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
>
> -    if (!(ri->type & ARM_CP_NO_MIGRATE)) {
> +    if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
>          cpu->cpreg_array_len++;
>      }
>  }
> @@ -508,7 +508,7 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
>        .resetvalue = 0 },
>      /* v6 doesn't have the cache ID registers but Linux reads them anyway
> */
>      { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 =
> CP_ANY,
> -      .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
> +      .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
>        .resetvalue = 0 },
>      /* We don't implement pre-v7 debug but most CPUs had at least a
> DBGDIDR;
>       * implementing it as RAZ means the "debug architecture version" bits
> @@ -522,16 +522,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
>       */
>      { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
>        .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn =
> tlbiall_write,
> -      .type = ARM_CP_NO_MIGRATE },
> +      .type = ARM_CP_NO_RAW },
>      { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
>        .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn =
> tlbimva_write,
> -      .type = ARM_CP_NO_MIGRATE },
> +      .type = ARM_CP_NO_RAW },
>      { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
>        .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn =
> tlbiasid_write,
> -      .type = ARM_CP_NO_MIGRATE },
> +      .type = ARM_CP_NO_RAW },
>      { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
>        .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn =
> tlbimvaa_write,
> -      .type = ARM_CP_NO_MIGRATE },
> +      .type = ARM_CP_NO_RAW },
>      REGINFO_SENTINEL
>  };
>
> @@ -854,7 +854,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>       * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
>       */
>      { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0,
> .opc2 = 1,
> -      .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL0_RW, .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
>        .writefn = pmcntenset_write,
>        .accessfn = pmreg_access,
> @@ -869,11 +869,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
>        .accessfn = pmreg_access,
>        .writefn = pmcntenclr_write,
> -      .type = ARM_CP_NO_MIGRATE },
> +      .type = ARM_CP_ALIAS },
>      { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
>        .access = PL0_RW, .accessfn = pmreg_access,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
>        .writefn = pmcntenclr_write },
>      { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 =
> 3,
> @@ -928,7 +928,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .resetvalue = 0,
>        .writefn = pmintenset_write, .raw_writefn = raw_write },
>      { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0,
> .opc2 = 2,
> -      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_RW, .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>        .resetvalue = 0, .writefn = pmintenclr_write, },
>      { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
> @@ -939,7 +939,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .resetvalue = 0 },
>      { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
> -      .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
> +      .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
>      { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
>        .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
> @@ -988,44 +988,44 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .resetfn = arm_cp_reset_ignore },
>      { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
> +      .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
>      /* 32 bit ITLB invalidates */
>      { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2
> = 0,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbiall_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
>      { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2
> = 1,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimva_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
>      { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2
> = 2,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbiasid_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
>      /* 32 bit DTLB invalidates */
>      { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2
> = 0,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbiall_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
>      { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2
> = 1,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimva_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
>      { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2
> = 2,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbiasid_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
>      /* 32 bit TLB invalidates */
>      { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 =
> 0,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbiall_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
>      { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 =
> 1,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimva_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
>      { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2
> = 2,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbiasid_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
>      { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2
> = 3,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimvaa_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
>      REGINFO_SENTINEL
>  };
>
>  static const ARMCPRegInfo v7mp_cp_reginfo[] = {
>      /* 32 bit TLB invalidates, Inner Shareable */
>      { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2
> = 0,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbiall_is_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write
> },
>      { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2
> = 1,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimva_is_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write
> },
>      { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3,
> .opc2 = 2,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
> +      .type = ARM_CP_NO_RAW, .access = PL1_W,
>        .writefn = tlbiasid_is_write },
>      { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3,
> .opc2 = 3,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
> +      .type = ARM_CP_NO_RAW, .access = PL1_W,
>        .writefn = tlbimvaa_is_write },
>      REGINFO_SENTINEL
>  };
> @@ -1268,7 +1268,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]
> = {
>       * Our reset value matches the fixed frequency we implement the timer
> at.
>       */
>      { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 =
> 0,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
>        .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
>        .resetfn = arm_cp_reset_ignore,
> @@ -1288,7 +1288,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]
> = {
>      },
>      /* per-timer control */
>      { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2
> = 1,
> -      .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
>        .accessfn = gt_ptimer_access,
>        .fieldoffset = offsetoflow32(CPUARMState,
>                                     cp15.c14_timer[GTIMER_PHYS].ctl),
> @@ -1304,7 +1304,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]
> = {
>        .writefn = gt_ctl_write, .raw_writefn = raw_write,
>      },
>      { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2
> = 1,
> -      .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
>        .accessfn = gt_vtimer_access,
>        .fieldoffset = offsetoflow32(CPUARMState,
>                                     cp15.c14_timer[GTIMER_VIRT].ctl),
> @@ -1321,52 +1321,52 @@ static const ARMCPRegInfo
> generic_timer_cp_reginfo[] = {
>      },
>      /* TimerValue views: a 32 bit downcounting view of the underlying
> state */
>      { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0,
> .opc2 = 0,
> -      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
>

I realize there is no raw offset or raw*fn, but this register is marked
NO_RAW and yet it would satisfy the later patch's raw_accessors_valid
check?  It feels like something is missing here. There are other case of
this as well.


>        .accessfn = gt_ptimer_access,
>        .readfn = gt_tval_read, .writefn = gt_tval_write,
>      },
>      { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
> -      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,

       .readfn = gt_tval_read, .writefn = gt_tval_write,
>      },
>      { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0,
> .opc2 = 0,
> -      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
>        .accessfn = gt_vtimer_access,
>        .readfn = gt_tval_read, .writefn = gt_tval_write,
>      },
>      { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
> -      .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
> +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
>        .readfn = gt_tval_read, .writefn = gt_tval_write,
>      },
>      /* The counter itself */
>      { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
> -      .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE |
> ARM_CP_IO,
> +      .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
>        .accessfn = gt_pct_access,
>        .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
>      },
>      { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
> -      .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
> +      .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
>        .accessfn = gt_pct_access,
>        .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
>      },
>      { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
> -      .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE |
> ARM_CP_IO,
> +      .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
>        .accessfn = gt_vct_access,
>        .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
>      },
>      { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
> -      .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
> +      .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
>        .accessfn = gt_vct_access,
>        .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
>      },
>      /* Comparison value, indicating when the timer goes off */
>      { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
>        .access = PL1_RW | PL0_R,
> -      .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState,
> cp15.c14_timer[GTIMER_PHYS].cval),
>        .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
>        .writefn = gt_cval_write, .raw_writefn = raw_write,
> @@ -1381,7 +1381,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[]
> = {
>      },
>      { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
>        .access = PL1_RW | PL0_R,
> -      .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState,
> cp15.c14_timer[GTIMER_VIRT].cval),
>        .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
>        .writefn = gt_cval_write, .raw_writefn = raw_write,
> @@ -1428,7 +1428,7 @@ static CPAccessResult ats_access(CPUARMState *env,
> const ARMCPRegInfo *ri)
>          /* Other states are only available with TrustZone; in
>           * a non-TZ implementation these registers don't exist
>           * at all, which is an Uncategorized trap. This underdecoding
> -         * is safe because the reginfo is NO_MIGRATE.
> +         * is safe because the reginfo is NO_RAW.
>           */
>          return CP_ACCESS_TRAP_UNCATEGORIZED;
>      }
> @@ -1495,7 +1495,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
>  #ifndef CONFIG_USER_ONLY
>      { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 =
> CP_ANY,
>        .access = PL1_W, .accessfn = ats_access,
> -      .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
> +      .writefn = ats_write, .type = ARM_CP_NO_RAW },
>  #endif
>      REGINFO_SENTINEL
>  };
> @@ -1554,12 +1554,12 @@ static uint64_t pmsav5_insn_ap_read(CPUARMState
> *env, const ARMCPRegInfo *ri)
>
>  static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
>      { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 =
> 0,
> -      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_RW, .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
>        .resetvalue = 0,
>        .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
>      { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 =
> 1,
> -      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_RW, .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
>        .resetvalue = 0,
>        .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
> @@ -1691,7 +1691,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
>
>  static const ARMCPRegInfo vmsa_cp_reginfo[] = {
>      { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_RW, .type = ARM_CP_ALIAS,
>

Not necessarily related to this change, but there may be a bug here.
Clearly, the NS bank gets handled by the ESR_EL1 registration.  In the case
of the secure bank, the expectation is that the ESR_EL3 registration takes
care of it but it is only registered as part of the v8 reg set. In which
case, I don't think that the secure bank will get migrated on v7 with EL3
enabled.


>        .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
>                               offsetoflow32(CPUARMState, cp15.dfsr_ns) },
>        .resetfn = arm_cp_reset_ignore, },
> @@ -1719,7 +1719,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
>        .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
>      { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
> -      .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn =
> vmsa_ttbcr_write,
> +      .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
>        .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
>        .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
>                               offsetoflow32(CPUARMState, cp15.tcr_el[1])}
> },
> @@ -1789,7 +1789,7 @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
>        .writefn = omap_threadid_write },
>      { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
>        .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_NO_RAW,
>        .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
>      /* TODO: Peripheral port remap register:
>       * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
> controller
> @@ -1798,7 +1798,7 @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
>       */
>      { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
>        .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
> -      .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
>        .writefn = omap_cachemaint_write },
>      { .name = "C9", .cp = 15, .crn = 9,
>        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
> @@ -1848,7 +1848,7 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
>      { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
>        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
>        .access = PL1_RW,
> -      .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
> +      .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
>        .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
> @@ -1856,7 +1856,7 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
>  static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
>      /* Cache status: RAZ because we have no cache so it's always clean */
>      { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
> -      .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
> +      .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
>        .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
> @@ -1864,7 +1864,7 @@ static const ARMCPRegInfo
> cache_dirty_status_cp_reginfo[] = {
>  static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
>      /* We never have a a block transfer operation in progress */
>      { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
> -      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
> +      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
>        .resetvalue = 0 },
>      /* The cache ops themselves: these all NOP for QEMU */
>      { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
> @@ -1887,10 +1887,10 @@ static const ARMCPRegInfo
> cache_test_clean_cp_reginfo[] = {
>       * to indicate that there are no dirty cache lines.
>       */
>      { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0,
> .opc2 = 3,
> -      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
> +      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
>        .resetvalue = (1 << 30) },
>      { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0,
> .opc2 = 3,
> -      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
> +      .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
>        .resetvalue = (1 << 30) },
>      REGINFO_SENTINEL
>  };
> @@ -1900,7 +1900,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
>      { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
>        .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
>        .access = PL1_RW, .resetvalue = 0,
> -      .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
> +      .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
>      REGINFO_SENTINEL
>  };
>
> @@ -1926,7 +1926,7 @@ static uint64_t mpidr_read(CPUARMState *env, const
> ARMCPRegInfo *ri)
>  static const ARMCPRegInfo mpidr_cp_reginfo[] = {
>      { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
> -      .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
> +      .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
>      REGINFO_SENTINEL
>  };
>
> @@ -1947,12 +1947,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
>        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
>                               offsetof(CPUARMState, cp15.par_ns)} },
>      { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
> -      .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
> +      .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
>        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
>                               offsetof(CPUARMState, cp15.ttbr0_ns) },
>        .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
>      { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
> -      .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
> +      .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
>        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
>                               offsetof(CPUARMState, cp15.ttbr1_ns) },
>        .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
> @@ -2144,7 +2144,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>        .access = PL0_RW, .type = ARM_CP_NZCV },
>      { .name = "DAIF", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_NO_RAW,
>        .access = PL0_RW, .accessfn = aa64_daif_access,
>        .fieldoffset = offsetof(CPUARMState, daif),
>        .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
> @@ -2156,7 +2156,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>        .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn =
> aa64_fpsr_write },
>      { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
> -      .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL0_R, .type = ARM_CP_NO_RAW,
>        .readfn = aa64_dczid_read },
>      { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
> @@ -2207,77 +2207,77 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>      /* TLBI operations */
>      { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbiall_is_write },
>      { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_va_is_write },
>      { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_asid_is_write },
>      { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_vaa_is_write },
>      { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_va_is_write },
>      { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_vaa_is_write },
>      { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbiall_write },
>      { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_va_write },
>      { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_asid_write },
>      { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_vaa_write },
>      { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_va_write },
>      { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> +      .access = PL1_W, .type = ARM_CP_NO_RAW,
>        .writefn = tlbi_aa64_vaa_write },
>  #ifndef CONFIG_USER_ONLY
>      /* 64 bit address translation operations */
>      { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
> +      .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write },
>      { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
> +      .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write },
>      { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
> +      .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write },
>      { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
>        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
> -      .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
> +      .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write },
>  #endif
>      /* TLB invalidate last level of translation table walk */
>      { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3,
> .opc2 = 5,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimva_is_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write
> },
>      { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3,
> .opc2 = 7,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
> +      .type = ARM_CP_NO_RAW, .access = PL1_W,
>        .writefn = tlbimvaa_is_write },
>      { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2
> = 5,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimva_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
>      { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2
> = 7,
> -      .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn =
> tlbimvaa_write },
> +      .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
>      /* 32 bit cache operations */
>      { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2
> = 0,
>        .type = ARM_CP_NOP, .access = PL1_W },
> @@ -2312,12 +2312,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>        .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
>                               offsetoflow32(CPUARMState, cp15.dacr_ns) } },
>      { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
>        .access = PL1_RW,
>        .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
>      { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
>        .access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
> banked_spsr[0]) },
>      /* We rely on the access checks not allowing the guest to write to the
> @@ -2327,11 +2327,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>      { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
>        .access = PL1_RW, .accessfn = sp_el0_access,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
>      { .name = "SPSel", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_NO_RAW,
>        .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
>      REGINFO_SENTINEL
>  };
> @@ -2343,7 +2343,7 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[]
> = {
>        .access = PL2_RW,
>        .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
>      { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_NO_RAW,
>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
>        .access = PL2_RW,
>        .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
> @@ -2386,12 +2386,12 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
>        .writefn = dacr_write, .raw_writefn = raw_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
>      { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
>        .access = PL2_RW,
>        .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
>      { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.esr_el[2]) },
>      { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
> @@ -2402,7 +2402,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.far_el[2]) },
>      { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
> banked_spsr[6]) },
>      { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
> @@ -2428,19 +2428,19 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
>        .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
>      { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
>        .access = PL3_RW,
>        .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
>      { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
>        .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.esr_el[3]) },
>      { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
>        .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.far_el[3]) },
>      { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
>        .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> banked_spsr[7]) },
>      { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
> @@ -2456,7 +2456,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
>        .access = PL3_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.scr_el3),
>        .resetvalue = 0, .writefn = scr_write },
> -    { .name = "SCR",  .type = ARM_CP_NO_MIGRATE,
> +    { .name = "SCR",  .type = ARM_CP_ALIAS,
>        .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
>        .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
> cp15.scr_el3),
>        .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
> @@ -2514,7 +2514,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
>       */
>      { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
>        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
> -      .type = ARM_CP_NO_MIGRATE,
> +      .type = ARM_CP_ALIAS,
>        .access = PL1_R,
>        .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
>        .resetfn = arm_cp_reset_ignore },
> @@ -2967,7 +2967,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          ARMCPRegInfo pmcr = {
>              .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0,
> .opc2 = 0,
>              .access = PL0_RW,
> -            .type = ARM_CP_IO | ARM_CP_NO_MIGRATE,
> +            .type = ARM_CP_IO | ARM_CP_ALIAS,
>              .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
>              .accessfn = pmreg_access, .writefn = pmcr_write,
>              .raw_writefn = raw_write,
> @@ -3447,14 +3447,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu,
> const ARMCPRegInfo *r,
>               */
>              if ((r->state == ARM_CP_STATE_BOTH && ns) ||
>                  (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
> -                r2->type |= ARM_CP_NO_MIGRATE;
> +                r2->type |= ARM_CP_ALIAS;
>                  r2->resetfn = arm_cp_reset_ignore;
>              }
>          } else if ((secstate != r->secure) && !ns) {
>              /* The register is not banked so we only want to allow
> migration of
>               * the non-secure instance.
>               */
> -            r2->type |= ARM_CP_NO_MIGRATE;
> +            r2->type |= ARM_CP_ALIAS;
>              r2->resetfn = arm_cp_reset_ignore;
>          }
>
> @@ -3503,15 +3503,17 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu,
> const ARMCPRegInfo *r,
>      r2->opc2 = opc2;
>      /* By convention, for wildcarded registers only the first
>       * entry is used for migration; the others are marked as
> -     * NO_MIGRATE so we don't try to transfer the register
> +     * ALIAS so we don't try to transfer the register
>       * multiple times. Special registers (ie NOP/WFI) are
> -     * never migratable.
> +     * never migratable and not even raw-accessible.
>       */
> -    if ((r->type & ARM_CP_SPECIAL) ||
> -        ((r->crm == CP_ANY) && crm != 0) ||
> +    if ((r->type & ARM_CP_SPECIAL)) {
> +        r2->type |= ARM_CP_NO_RAW;
> +    }
> +    if (((r->crm == CP_ANY) && crm != 0) ||
>          ((r->opc1 == CP_ANY) && opc1 != 0) ||
>          ((r->opc2 == CP_ANY) && opc2 != 0)) {
> -        r2->type |= ARM_CP_NO_MIGRATE;
> +        r2->type |= ARM_CP_ALIAS;
>      }
>
>      /* Overriding of an existing definition must be explicitly
> --
> 1.9.1
>
>
>
It's not always the case in the code, but wouldn't it also be true that any
register marked ARM_CP_CONST should also be ARM_CP_RAW?

--001a113349086c74810509e3ccd3
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr"><br><div class=3D"gmail_extra"><br><div class=3D"gmail_quo=
te">On 9 December 2014 at 13:46, Peter Maydell <span dir=3D"ltr">&lt;<a hre=
f=3D"mailto:peter.maydell@linaro.org" target=3D"_blank">peter.maydell@linar=
o.org</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" style=3D"m=
argin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">We currently =
mark ARM coprocessor/system register definitions with<br>
the flag ARM_CP_NO_MIGRATE for two different reasons:<br>
1) register is an alias on to state that&#39;s also visible via<br>
=C2=A0 =C2=A0some other register, and that other register is the one<br>
=C2=A0 =C2=A0responsible for migrating the state<br>
2) register is not actually state at all (for instance the TLB<br>
=C2=A0 =C2=A0or cache maintenance operation &quot;registers&quot;) and it m=
akes no<br>
=C2=A0 =C2=A0sense to attempt to migrate it or otherwise access the raw sta=
te<br>
<br>
This works fine for identifying which registers should be ignored<br>
when performing migration, but we also use the same functions for<br>
synchronizing system register state between QEMU and the kernel<br>
when using KVM. In this case we don&#39;t want to try to sync state<br>
into registers in category 2, but we do want to sync into registers<br>
in category 1, because the kernel might have picked a different<br>
one of the aliases as its choice for which one to expose for<br>
migration. (In particular, on 32 bit hosts the kernel will<br>
expose the state in the AArch32 version of the register, but<br>
TCG&#39;s convention is to mark the AArch64 version as the version<br>
to migrate, even if the CPU being emulated happens to be 32 bit,<br>
so almost all system registers will hit this issue now that we&#39;ve<br>
added AArch64 system emulation.)<br>
<br>
Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW)<br>
corresponding to the two different reasons we might not want to<br>
migrate a register. When setting up the TCG list of registers to<br>
migrate we honour both flags; when populating the list from KVM,<br>
only ignore registers which are NO_RAW.<br>
<br>
Signed-off-by: Peter Maydell &lt;<a href=3D"mailto:peter.maydell@linaro.org=
">peter.maydell@linaro.org</a>&gt;<br>
---<br>
=C2=A0target-arm/cpu.h=C2=A0 =C2=A0 |=C2=A0 15 +++-<br>
=C2=A0target-arm/helper.c | 206 ++++++++++++++++++++++++++-----------------=
---------<br>
=C2=A02 files changed, 115 insertions(+), 106 deletions(-)<br>
<br>
diff --git a/target-arm/cpu.h b/target-arm/cpu.h<br>
index 7ba55f0..831a841 100644<br>
--- a/target-arm/cpu.h<br>
+++ b/target-arm/cpu.h<br>
@@ -1112,8 +1112,14 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpre=
gid)<br>
=C2=A0 * a register definition to override a previous definition for the<br=
>
=C2=A0 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the=
<br>
=C2=A0 * old must have the OVERRIDE bit set.<br>
- * NO_MIGRATE indicates that this register should be ignored for migration=
;<br>
- * (eg because any state is accessed via some other coprocessor register).=
<br>
+ * ALIAS indicates that this register is an alias view of some underlying<=
br>
+ * state which is also visible via another register, and that the other<br=
>
+ * register is handling migration; registers marked ALIAS will not be migr=
ated<br>
+ * but may have their state set by syncing of register state from KVM.<br>
+ * NO_RAW indicates that this register has no underlying state and does no=
t<br>
+ * support raw access for state saving/loading; it will not be used for ei=
ther<br>
+ * migration or KVM state synchronization. (Typically this is for &quot;re=
gisters&quot;<br>
+ * which are actually used as instructions for cache maintenance and so on=
.)<br>
=C2=A0 * IO indicates that this register does I/O and therefore its accesse=
s<br>
=C2=A0 * need to be surrounded by gen_io_start()/gen_io_end(). In particula=
r,<br>
=C2=A0 * registers which implement clocks or timers require this.<br>
@@ -1123,8 +1129,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg=
id)<br>
=C2=A0#define ARM_CP_64BIT 4<br>
=C2=A0#define ARM_CP_SUPPRESS_TB_END 8<br>
=C2=A0#define ARM_CP_OVERRIDE 16<br>
-#define ARM_CP_NO_MIGRATE 32<br>
+#define ARM_CP_ALIAS 32<br>
=C2=A0#define ARM_CP_IO 64<br>
+#define ARM_CP_NO_RAW 128<br>
=C2=A0#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 &lt;&lt; 8))<br>
=C2=A0#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 &lt;&lt; 8))<br>
=C2=A0#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 &lt;&lt; 8))<br>
@@ -1134,7 +1141,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg=
id)<br>
=C2=A0/* Used only as a terminator for ARMCPRegInfo lists */<br>
=C2=A0#define ARM_CP_SENTINEL 0xffff<br>
=C2=A0/* Mask of only the flag bits in a type field */<br>
-#define ARM_CP_FLAG_MASK 0x7f<br>
+#define ARM_CP_FLAG_MASK 0xff<br>
<br>
=C2=A0/* Valid values for ARMCPRegInfo state field, indicating which of<br>
=C2=A0 * the AArch32 and AArch64 execution states this register is visible =
in.<br>
diff --git a/target-arm/helper.c b/target-arm/helper.c<br>
index 96abbed..d1b856c 100644<br>
--- a/target-arm/helper.c<br>
+++ b/target-arm/helper.c<br>
@@ -189,7 +189,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ok =3D false;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0continue;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ri-&gt;type &amp; ARM_CP_NO_MIGRATE) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ri-&gt;type &amp; ARM_CP_NO_RAW) {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0continue;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu-&gt;cpreg_values[i] =3D read_raw_cp_r=
eg(&amp;cpu-&gt;env, ri);<br>
@@ -212,7 +212,7 @@ bool write_list_to_cpustate(ARMCPU *cpu)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ok =3D false;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0continue;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ri-&gt;type &amp; ARM_CP_NO_MIGRATE) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ri-&gt;type &amp; ARM_CP_NO_RAW) {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0continue;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Write value and confirm it reads back =
as written<br>
@@ -236,7 +236,7 @@ static void add_cpreg_to_list(gpointer key, gpointer op=
aque)<br>
=C2=A0 =C2=A0 =C2=A0regidx =3D *(uint32_t *)key;<br>
=C2=A0 =C2=A0 =C2=A0ri =3D get_arm_cp_reginfo(cpu-&gt;cp_regs, regidx);<br>
<br>
-=C2=A0 =C2=A0 if (!(ri-&gt;type &amp; ARM_CP_NO_MIGRATE)) {<br>
+=C2=A0 =C2=A0 if (!(ri-&gt;type &amp; (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu-&gt;cpreg_indexes[cpu-&gt;cpreg_array=
_len] =3D cpreg_to_kvm_id(regidx);<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* The value array need not be initialize=
d at this point */<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu-&gt;cpreg_array_len++;<br>
@@ -252,7 +252,7 @@ static void count_cpreg(gpointer key, gpointer opaque)<=
br>
=C2=A0 =C2=A0 =C2=A0regidx =3D *(uint32_t *)key;<br>
=C2=A0 =C2=A0 =C2=A0ri =3D get_arm_cp_reginfo(cpu-&gt;cp_regs, regidx);<br>
<br>
-=C2=A0 =C2=A0 if (!(ri-&gt;type &amp; ARM_CP_NO_MIGRATE)) {<br>
+=C2=A0 =C2=A0 if (!(ri-&gt;type &amp; (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu-&gt;cpreg_array_len++;<br>
=C2=A0 =C2=A0 =C2=A0}<br>
=C2=A0}<br>
@@ -508,7 +508,7 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },<br>
=C2=A0 =C2=A0 =C2=A0/* v6 doesn&#39;t have the cache ID registers but Linux=
 reads them anyway */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DUMMY&quot;, .cp =3D 15, .crn =3D 0, =
.crm =3D 0, .opc1 =3D 1, .opc2 =3D CP_ANY,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },<br>
=C2=A0 =C2=A0 =C2=A0/* We don&#39;t implement pre-v7 debug but most CPUs ha=
d at least a DBGDIDR;<br>
=C2=A0 =C2=A0 =C2=A0 * implementing it as RAZ means the &quot;debug archite=
cture version&quot; bits<br>
@@ -522,16 +522,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D {<b=
r>
=C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIALL&quot;, .cp =3D 15, .crn =3D 8=
, .crm =3D CP_ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W=
, .writefn =3D tlbiall_write,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVA&quot;, .cp =3D 15, .crn =3D 8=
, .crm =3D CP_ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W=
, .writefn =3D tlbimva_write,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIASID&quot;, .cp =3D 15, .crn =3D =
8, .crm =3D CP_ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W=
, .writefn =3D tlbiasid_write,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVAA&quot;, .cp =3D 15, .crn =3D =
8, .crm =3D CP_ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W=
, .writefn =3D tlbimvaa_write,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
<br>
@@ -854,7 +854,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 * or PL0_RO as appropriate and then check PMUSERENR in=
 the helper fn.<br>
=C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;PMCNTENSET&quot;, .cp =3D 15, .crn =
=3D 9, .crm =3D 12, .opc1 =3D 0, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_RW, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_RW, .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15=
.c9_pmcnten),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D pmcntenset_write,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D pmreg_access,<br>
@@ -869,11 +869,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15=
.c9_pmcnten),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D pmreg_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D pmcntenclr_write,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;PMCNTENCLR_EL0&quot;, .state =3D ARM_=
CP_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 1=
2, .opc2 =3D 2,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW, .accessfn =3D pmreg_access,<=
br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.c9_p=
mcnten),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D pmcntenclr_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;PMOVSR&quot;, .cp =3D 15, .crn =3D 9,=
 .crm =3D 12, .opc1 =3D 0, .opc2 =3D 3,<br>
@@ -928,7 +928,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D pmintenset_write, .raw_writefn =3D =
raw_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;PMINTENCLR&quot;, .cp =3D 15, .crn =
=3D 9, .crm =3D 14, .opc1 =3D 0, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.c9_p=
minten),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0, .writefn =3D pmintenclr_write=
, },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;VBAR&quot;, .state =3D ARM_CP_STATE_B=
OTH,<br>
@@ -939,7 +939,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CCSIDR&quot;, .state =3D ARM_CP_STATE=
_BOTH,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1=
, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .readfn =3D ccsidr_read, .type =3D=
 ARM_CP_NO_MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .readfn =3D ccsidr_read, .type =3D=
 ARM_CP_NO_RAW },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CSSELR&quot;, .state =3D ARM_CP_STATE=
_BOTH,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .writefn =3D csselr_write, .=
resetvalue =3D 0,<br>
@@ -988,44 +988,44 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ISR_EL1&quot;, .state =3D ARM_CP_STAT=
E_BOTH,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D =
1, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_R, .read=
fn =3D isr_read },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =
=3D isr_read },<br>
=C2=A0 =C2=A0 =C2=A0/* 32 bit ITLB invalidates */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ITLBIALL&quot;, .cp =3D 15, .opc1 =3D=
 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbiall_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbiall_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ITLBIMVA&quot;, .cp =3D 15, .opc1 =3D=
 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimva_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimva_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ITLBIASID&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbiasid_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbiasid_write },<br>
=C2=A0 =C2=A0 =C2=A0/* 32 bit DTLB invalidates */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DTLBIALL&quot;, .cp =3D 15, .opc1 =3D=
 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbiall_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbiall_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DTLBIMVA&quot;, .cp =3D 15, .opc1 =3D=
 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimva_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimva_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DTLBIASID&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbiasid_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbiasid_write },<br>
=C2=A0 =C2=A0 =C2=A0/* 32 bit TLB invalidates */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIALL&quot;, .cp =3D 15, .opc1 =3D =
0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbiall_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbiall_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVA&quot;, .cp =3D 15, .opc1 =3D =
0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimva_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimva_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIASID&quot;, .cp =3D 15, .opc1 =3D=
 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbiasid_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbiasid_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVAA&quot;, .cp =3D 15, .opc1 =3D=
 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimvaa_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimvaa_write },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
<br>
=C2=A0static const ARMCPRegInfo v7mp_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0/* 32 bit TLB invalidates, Inner Shareable */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIALLIS&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbiall_is_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbiall_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVAIS&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimva_is_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimva_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIASIDIS&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbiasid_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVAAIS&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbimvaa_is_write },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
@@ -1268,7 +1268,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] =
=3D {<br>
=C2=A0 =C2=A0 =C2=A0 * Our reset value matches the fixed frequency we imple=
ment the timer at.<br>
=C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTFRQ&quot;, .cp =3D 15, .crn =3D 14=
, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW | PL0_R, .accessfn =3D gt_cnt=
frq_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15=
.c14_cntfrq),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore,<br>
@@ -1288,7 +1288,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] =
=3D {<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0/* per-timer control */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTP_CTL&quot;, .cp =3D 15, .crn =3D =
14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_IO | ARM_CP_NO_MIGRATE, .access =3D =
PL1_RW | PL0_R,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_R=
W | PL0_R,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_ptimer_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cp15.c14_timer[GTIMER_=
PHYS].ctl),<br>
@@ -1304,7 +1304,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] =
=3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D gt_ctl_write, .raw_writefn =3D raw_=
write,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTV_CTL&quot;, .cp =3D 15, .crn =3D =
14, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_IO | ARM_CP_NO_MIGRATE, .access =3D =
PL1_RW | PL0_R,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_R=
W | PL0_R,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_vtimer_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cp15.c14_timer[GTIMER_=
VIRT].ctl),<br>
@@ -1321,52 +1321,52 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[=
] =3D {<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0/* TimerValue views: a 32 bit downcounting view of the =
underlying state */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTP_TVAL&quot;, .cp =3D 15, .crn =3D=
 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE | ARM_CP_IO, .access =3D =
PL1_RW | PL0_R,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_=
RW | PL0_R,<br></blockquote><div><br></div><div>I realize there is no raw o=
ffset or raw*fn, but this register is marked NO_RAW and yet it would satisf=
y the later patch&#39;s raw_accessors_valid check?=C2=A0 It feels like some=
thing is missing here. There are other case of this as well.</div><div>=C2=
=A0</div><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;borde=
r-left:1px #ccc solid;padding-left:1ex">
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_ptimer_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_tval_read, .writefn =3D gt_tval_w=
rite,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTP_TVAL_EL0&quot;, .state =3D ARM_C=
P_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D =
2, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE | ARM_CP_IO, .access =3D =
PL1_RW | PL0_R,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_=
RW | PL0_R,</blockquote><blockquote class=3D"gmail_quote" style=3D"margin:0=
 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_tval_read, .writefn =3D gt_tval_w=
rite,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTV_TVAL&quot;, .cp =3D 15, .crn =3D=
 14, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE | ARM_CP_IO, .access =3D =
PL1_RW | PL0_R,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_=
RW | PL0_R,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_vtimer_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_tval_read, .writefn =3D gt_tval_w=
rite,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTV_TVAL_EL0&quot;, .state =3D ARM_C=
P_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D =
3, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE | ARM_CP_IO, .access =3D =
PL1_RW | PL0_R,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_=
RW | PL0_R,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_tval_read, .writefn =3D gt_tval_w=
rite,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0/* The counter itself */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTPCT&quot;, .cp =3D 15, .crm =3D 14=
, .opc1 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO=
_MIGRATE | ARM_CP_IO,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO=
_RAW | ARM_CP_IO,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_pct_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_cnt_read, .resetfn =3D arm_cp_res=
et_ignore,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTPCT_EL0&quot;, .state =3D ARM_CP_S=
TATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D =
0, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_NO_MIGRATE | ARM_=
CP_IO,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_I=
O,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_pct_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_cnt_read, .resetfn =3D gt_cnt_res=
et,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTVCT&quot;, .cp =3D 15, .crm =3D 14=
, .opc1 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO=
_MIGRATE | ARM_CP_IO,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO=
_RAW | ARM_CP_IO,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_vct_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_cnt_read, .resetfn =3D arm_cp_res=
et_ignore,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTVCT_EL0&quot;, .state =3D ARM_CP_S=
TATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D =
0, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_NO_MIGRATE | ARM_=
CP_IO,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_I=
O,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_vct_access,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D gt_cnt_read, .resetfn =3D gt_cnt_res=
et,<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0/* Comparison value, indicating when the timer goes off=
 */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTP_CVAL&quot;, .cp =3D 15, .crm =3D=
 14, .opc1 =3D 2,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW | PL0_R,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRAT=
E,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,<br=
>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.c14_=
timer[GTIMER_PHYS].cval),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_ptimer_access, .resetfn =3D arm=
_cp_reset_ignore,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D gt_cval_write, .raw_writefn =3D raw=
_write,<br>
@@ -1381,7 +1381,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] =
=3D {<br>
=C2=A0 =C2=A0 =C2=A0},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CNTV_CVAL&quot;, .cp =3D 15, .crm =3D=
 14, .opc1 =3D 3,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW | PL0_R,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRAT=
E,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,<br=
>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.c14_=
timer[GTIMER_VIRT].cval),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D gt_vtimer_access, .resetfn =3D arm=
_cp_reset_ignore,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D gt_cval_write, .raw_writefn =3D raw=
_write,<br>
@@ -1428,7 +1428,7 @@ static CPAccessResult ats_access(CPUARMState *env, co=
nst ARMCPRegInfo *ri)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Other states are only available with T=
rustZone; in<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * a non-TZ implementation these register=
s don&#39;t exist<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * at all, which is an Uncategorized trap=
. This underdecoding<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* is safe because the reginfo is NO_MIGR=
ATE.<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* is safe because the reginfo is NO_RAW.=
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return CP_ACCESS_TRAP_UNCATEGORIZED;<br>
=C2=A0 =C2=A0 =C2=A0}<br>
@@ -1495,7 +1495,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] =3D {<br>
=C2=A0#ifndef CONFIG_USER_ONLY<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ATS&quot;, .cp =3D 15, .crn =3D 7, .c=
rm =3D 8, .opc1 =3D 0, .opc2 =3D CP_ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_W, .accessfn =3D ats_access,<br>
-=C2=A0 =C2=A0 =C2=A0 .writefn =3D ats_write, .type =3D ARM_CP_NO_MIGRATE }=
,<br>
+=C2=A0 =C2=A0 =C2=A0 .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW },<br=
>
=C2=A0#endif<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
@@ -1554,12 +1554,12 @@ static uint64_t pmsav5_insn_ap_read(CPUARMState *en=
v, const ARMCPRegInfo *ri)<br>
<br>
=C2=A0static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DATA_AP&quot;, .cp =3D 15, .crn =3D 5=
, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.pmsa=
v5_data_ap),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D pmsav5_data_ap_read, .writefn =3D pm=
sav5_data_ap_write, },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;INSN_AP&quot;, .cp =3D 15, .crn =3D 5=
, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.pmsa=
v5_insn_ap),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D pmsav5_insn_ap_read, .writefn =3D pm=
sav5_insn_ap_write, },<br>
@@ -1691,7 +1691,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const A=
RMCPRegInfo *ri,<br>
<br>
=C2=A0static const ARMCPRegInfo vmsa_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DFSR&quot;, .cp =3D 15, .crn =3D 5, .=
crm =3D 0, .opc1 =3D 0, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_ALIAS,<br></bloc=
kquote><div><br></div><div>Not necessarily related to this change, but ther=
e may be a bug here.=C2=A0 Clearly, the NS bank gets handled by the ESR_EL1=
 registration.=C2=A0 In the case of the secure bank, the expectation is tha=
t the ESR_EL3 registration takes care of it but it is only registered as pa=
rt of the v8 reg set. In which case, I don&#39;t think that the secure bank=
 will get migrated on v7 with EL3 enabled.</div><div>=C2=A0</div><blockquot=
e class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc sol=
id;padding-left:1ex">
=C2=A0 =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetoflow32(CPUARMSta=
te, cp15.dfsr_s),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offsetoflow32(CPUARMState, cp15.dfsr_ns) },=
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore, },<br>
@@ -1719,7 +1719,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D =
raw_write,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.tcr_=
el[1]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TTBCR&quot;, .cp =3D 15, .crn =3D 2, =
.crm =3D 0, .opc1 =3D 0, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_NO_MIGRATE, .wri=
tefn =3D vmsa_ttbcr_write,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, .writefn =
=3D vmsa_ttbcr_write,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore, .raw_writefn =
=3D vmsa_ttbcr_raw_write,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetoflow32(CPUARMSta=
te, cp15.tcr_el[3]),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offsetoflow32(CPUARMState, cp15.tcr_el[1])}=
 },<br>
@@ -1789,7 +1789,7 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D omap_threadid_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TI925T_STATUS&quot;, .cp =3D 15, .crn=
 =3D 15,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =
=3D PL1_RW,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D arm_cp_read_zero, .writefn =3D omap_=
wfi_write, },<br>
=C2=A0 =C2=A0 =C2=A0/* TODO: Peripheral port remap register:<br>
=C2=A0 =C2=A0 =C2=A0 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the inte=
rrupt controller<br>
@@ -1798,7 +1798,7 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;OMAP_CACHEMAINT&quot;, .cp =3D 15, .c=
rn =3D 7, .crm =3D CP_ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W=
,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D omap_cachemaint_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;C9&quot;, .cp =3D 15, .crn =3D 9,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_=
ANY, .access =3D PL1_RW,<br>
@@ -1848,7 +1848,7 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D =
{<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;C15_IMPDEF&quot;, .cp =3D 15, .crn =
=3D 15,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_=
ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_O=
VERRIDE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERR=
IDE,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
@@ -1856,7 +1856,7 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D =
{<br>
=C2=A0static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0/* Cache status: RAZ because we have no cache so it&#39=
;s always clean */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;CDSR&quot;, .cp =3D 15, .crn =3D 7, .=
crm =3D 10, .opc1 =3D 0, .opc2 =3D 6,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
@@ -1864,7 +1864,7 @@ static const ARMCPRegInfo cache_dirty_status_cp_regin=
fo[] =3D {<br>
=C2=A0static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0/* We never have a a block transfer operation in progre=
ss */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;BXSR&quot;, .cp =3D 15, .crn =3D 7, .=
crm =3D 12, .opc1 =3D 0, .opc2 =3D 4,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0 },<br>
=C2=A0 =C2=A0 =C2=A0/* The cache ops themselves: these all NOP for QEMU */<=
br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;IICR&quot;, .cp =3D 15, .crm =3D 5, .=
opc1 =3D 0,<br>
@@ -1887,10 +1887,10 @@ static const ARMCPRegInfo cache_test_clean_cp_regin=
fo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 * to indicate that there are no dirty cache lines.<br>
=C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TC_DCACHE&quot;, .cp =3D 15, .crn =3D=
 7, .crm =3D 10, .opc1 =3D 0, .opc2 =3D 3,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D (1 &lt;&lt; 30) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TCI_DCACHE&quot;, .cp =3D 15, .crn =
=3D 7, .crm =3D 14, .opc1 =3D 0, .opc2 =3D 3,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO=
_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D (1 &lt;&lt; 30) },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
@@ -1900,7 +1900,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D =
{<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;C9_READBUFFER&quot;, .cp =3D 15, .crn=
 =3D 9,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_=
ANY,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .resetvalue =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_=
MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_=
RAW },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
<br>
@@ -1926,7 +1926,7 @@ static uint64_t mpidr_read(CPUARMState *env, const AR=
MCPRegInfo *ri)<br>
=C2=A0static const ARMCPRegInfo mpidr_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;MPIDR&quot;, .state =3D ARM_CP_STATE_=
BOTH,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0=
, .opc2 =3D 5,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D =
ARM_CP_NO_MIGRATE },<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D =
ARM_CP_NO_RAW },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
<br>
@@ -1947,12 +1947,12 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D {<b=
r>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetof(CPUARMState, c=
p15.par_s),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offsetof(CPUARMState, cp15.par_ns)} },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TTBR0&quot;, .cp =3D 15, .crm =3D 2, =
.opc1 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_N=
O_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_A=
LIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetof(CPUARMState, c=
p15.ttbr0_s),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offsetof(CPUARMState, cp15.ttbr0_ns) },<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D vmsa_ttbr_write, .resetfn =3D arm_c=
p_reset_ignore },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TTBR1&quot;, .cp =3D 15, .crm =3D 2, =
.opc1 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_N=
O_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_A=
LIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetof(CPUARMState, c=
p15.ttbr1_s),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offsetof(CPUARMState, cp15.ttbr1_ns) },<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D vmsa_ttbr_write, .resetfn =3D arm_c=
p_reset_ignore },<br>
@@ -2144,7 +2144,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW, .type =3D ARM_CP_NZCV },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DAIF&quot;, .state =3D ARM_CP_STATE_A=
A64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D =
4, .crm =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW, .accessfn =3D aa64_daif_acce=
ss,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, daif),<br=
>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D aa64_daif_write, .resetfn =3D arm_c=
p_reset_ignore },<br>
@@ -2156,7 +2156,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW, .readfn =3D aa64_fpsr_read, =
.writefn =3D aa64_fpsr_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DCZID_EL0&quot;, .state =3D ARM_CP_ST=
ATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D =
0, .crm =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL0_R, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D aa64_dczid_read },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;DC_ZVA&quot;, .state =3D ARM_CP_STATE=
_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4=
, .opc2 =3D 1,<br>
@@ -2207,77 +2207,77 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0/* TLBI operations */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VMALLE1IS&quot;, .state =3D ARM_=
CP_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3=
, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbiall_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VAE1IS&quot;, .state =3D ARM_CP_=
STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3=
, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_va_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_ASIDE1IS&quot;, .state =3D ARM_C=
P_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3=
, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_asid_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VAAE1IS&quot;, .state =3D ARM_CP=
_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3=
, .opc2 =3D 3,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_vaa_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VALE1IS&quot;, .state =3D ARM_CP=
_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3=
, .opc2 =3D 5,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_va_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VAALE1IS&quot;, .state =3D ARM_C=
P_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3=
, .opc2 =3D 7,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_vaa_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VMALLE1&quot;, .state =3D ARM_CP=
_STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbiall_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VAE1&quot;, .state =3D ARM_CP_ST=
ATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_va_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_ASIDE1&quot;, .state =3D ARM_CP_=
STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_asid_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VAAE1&quot;, .state =3D ARM_CP_S=
TATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 3,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_vaa_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VALE1&quot;, .state =3D ARM_CP_S=
TATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 5,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_va_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBI_VAALE1&quot;, .state =3D ARM_CP_=
STATE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7=
, .opc2 =3D 7,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbi_aa64_vaa_write },<br>
=C2=A0#ifndef CONFIG_USER_ONLY<br>
=C2=A0 =C2=A0 =C2=A0/* 64 bit address translation operations */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;AT_S1E1R&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8=
, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ=
efn =3D ats_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =
=3D ats_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;AT_S1E1W&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8=
, .opc2 =3D 1,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ=
efn =3D ats_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =
=3D ats_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;AT_S1E0R&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8=
, .opc2 =3D 2,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ=
efn =3D ats_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =
=3D ats_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;AT_S1E0W&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8=
, .opc2 =3D 3,<br>
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ=
efn =3D ats_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, .writefn =
=3D ats_write },<br>
=C2=A0#endif<br>
=C2=A0 =C2=A0 =C2=A0/* TLB invalidate last level of translation table walk =
*/<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVALIS&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimva_is_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimva_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVAALIS&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D tlbimvaa_is_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVAL&quot;, .cp =3D 15, .opc1 =3D=
 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimva_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimva_write },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;TLBIMVAAL&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE, .access =3D PL1_W, .writ=
efn =3D tlbimvaa_write },<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =
=3D tlbimvaa_write },<br>
=C2=A0 =C2=A0 =C2=A0/* 32 bit cache operations */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ICIALLUIS&quot;, .cp =3D 15, .opc1 =
=3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.type =3D ARM_CP_NOP, .access =3D PL1_W },<br>
@@ -2312,12 +2312,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetoflow32(CPUARMSta=
te, cp15.dacr_s),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 offsetoflow32(CPUARMState, cp15.dacr_ns) } =
},<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ELR_EL1&quot;, .state =3D ARM_CP_STAT=
E_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0=
, .opc2 =3D 1,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, elr_el[1]=
) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;SPSR_EL1&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .fieldoffset =3D offsetof(CP=
UARMState, banked_spsr[0]) },<br>
=C2=A0 =C2=A0 =C2=A0/* We rely on the access checks not allowing the guest =
to write to the<br>
@@ -2327,11 +2327,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;SP_EL0&quot;, .state =3D ARM_CP_STATE=
_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 1=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .accessfn =3D sp_el0_access,=
<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, sp_el[0])=
 },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;SPSel&quot;, .state =3D ARM_CP_STATE_=
AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2=
, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .readfn =3D spsel_read, .wri=
tefn =3D spsel_write },<br>
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL<br>
=C2=A0};<br>
@@ -2343,7 +2343,7 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] =
=3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D arm_cp_read_zero, .writefn =3D arm_c=
p_write_ignore },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;HCR_EL2&quot;, .state =3D ARM_CP_STAT=
E_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_RAW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.readfn =3D arm_cp_read_zero, .writefn =3D arm_c=
p_write_ignore },<br>
@@ -2386,12 +2386,12 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] =3D {=
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.writefn =3D dacr_write, .raw_writefn =3D raw_wr=
ite,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.dacr=
32_el2) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ELR_EL2&quot;, .state =3D ARM_CP_STAT=
E_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0=
, .opc2 =3D 1,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, elr_el[2]=
) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ESR_EL2&quot;, .state =3D ARM_CP_STAT=
E_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW, .fieldoffset =3D offsetof(CP=
UARMState, cp15.esr_el[2]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;IFSR32_EL2&quot;, .state =3D ARM_CP_S=
TATE_AA64,<br>
@@ -2402,7 +2402,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] =3D {<b=
r>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW, .fieldoffset =3D offsetof(CP=
UARMState, cp15.far_el[2]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;SPSR_EL2&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW, .fieldoffset =3D offsetof(CP=
UARMState, banked_spsr[6]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;VBAR_EL2&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
@@ -2428,19 +2428,19 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] =3D {=
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D =
raw_write,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.tcr_=
el[3]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ELR_EL3&quot;, .state =3D ARM_CP_STAT=
E_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0=
, .opc2 =3D 1,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, elr_el[3]=
) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;ESR_EL3&quot;, .state =3D ARM_CP_STAT=
E_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetof(CP=
UARMState, cp15.esr_el[3]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;FAR_EL3&quot;, .state =3D ARM_CP_STAT=
E_AA64,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetof(CP=
UARMState, cp15.far_el[3]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;SPSR_EL3&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetof(CP=
UARMState, banked_spsr[7]) },<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;VBAR_EL3&quot;, .state =3D ARM_CP_STA=
TE_AA64,<br>
@@ -2456,7 +2456,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1=
, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetof(CP=
UARMState, cp15.scr_el3),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0, .writefn =3D scr_write },<br>
-=C2=A0 =C2=A0 { .name =3D &quot;SCR&quot;,=C2=A0 .type =3D ARM_CP_NO_MIGRA=
TE,<br>
+=C2=A0 =C2=A0 { .name =3D &quot;SCR&quot;,=C2=A0 .type =3D ARM_CP_ALIAS,<b=
r>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1,=
 .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetoflow=
32(CPUARMState, cp15.scr_el3),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore, .writefn =3D s=
cr_write },<br>
@@ -2514,7 +2514,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D {<br=
>
=C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0{ .name =3D &quot;MDCCSR_EL0&quot;, .state =3D ARM_CP_S=
TATE_BOTH,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0=
, .crm =3D 1, .opc2 =3D 0,<br>
-=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_ALIAS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_R,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.mdsc=
r_el1),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore },<br>
@@ -2967,7 +2967,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ARMCPRegInfo pmcr =3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.name =3D &quot;PMCR&quot;,=
 .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0, .opc2 =3D 0,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW,<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_IO | ARM_CP_NO_=
MIGRATE,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_IO | ARM_CP_ALI=
AS,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflo=
w32(CPUARMState, cp15.c9_pmcr),<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.accessfn =3D pmreg_access,=
 .writefn =3D pmcr_write,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.raw_writefn =3D raw_write,=
<br>
@@ -3447,14 +3447,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con=
st ARMCPRegInfo *r,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 */<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if ((r-&gt;state =3D=3D ARM=
_CP_STATE_BOTH &amp;&amp; ns) ||<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(arm_feature(=
&amp;cpu-&gt;env, ARM_FEATURE_V8) &amp;&amp; !ns)) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 r2-&gt;type |=3D A=
RM_CP_NO_MIGRATE;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 r2-&gt;type |=3D A=
RM_CP_ALIAS;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0r2-&gt;resetf=
n =3D arm_cp_reset_ignore;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if ((secstate !=3D r-&gt;secure) &=
amp;&amp; !ns) {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* The register is not bank=
ed so we only want to allow migration of<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * the non-secure instance.=
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 */<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 r2-&gt;type |=3D ARM_CP_NO_MIGRA=
TE;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 r2-&gt;type |=3D ARM_CP_ALIAS;<b=
r>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0r2-&gt;resetfn =3D arm_cp_r=
eset_ignore;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
<br>
@@ -3503,15 +3503,17 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con=
st ARMCPRegInfo *r,<br>
=C2=A0 =C2=A0 =C2=A0r2-&gt;opc2 =3D opc2;<br>
=C2=A0 =C2=A0 =C2=A0/* By convention, for wildcarded registers only the fir=
st<br>
=C2=A0 =C2=A0 =C2=A0 * entry is used for migration; the others are marked a=
s<br>
-=C2=A0 =C2=A0 =C2=A0* NO_MIGRATE so we don&#39;t try to transfer the regis=
ter<br>
+=C2=A0 =C2=A0 =C2=A0* ALIAS so we don&#39;t try to transfer the register<b=
r>
=C2=A0 =C2=A0 =C2=A0 * multiple times. Special registers (ie NOP/WFI) are<b=
r>
-=C2=A0 =C2=A0 =C2=A0* never migratable.<br>
+=C2=A0 =C2=A0 =C2=A0* never migratable and not even raw-accessible.<br>
=C2=A0 =C2=A0 =C2=A0 */<br>
-=C2=A0 =C2=A0 if ((r-&gt;type &amp; ARM_CP_SPECIAL) ||<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 ((r-&gt;crm =3D=3D CP_ANY) &amp;&amp; crm !=3D=
 0) ||<br>
+=C2=A0 =C2=A0 if ((r-&gt;type &amp; ARM_CP_SPECIAL)) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r2-&gt;type |=3D ARM_CP_NO_RAW;<br>
+=C2=A0 =C2=A0 }<br>
+=C2=A0 =C2=A0 if (((r-&gt;crm =3D=3D CP_ANY) &amp;&amp; crm !=3D 0) ||<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0((r-&gt;opc1 =3D=3D CP_ANY) &amp;&amp; op=
c1 !=3D 0) ||<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0((r-&gt;opc2 =3D=3D CP_ANY) &amp;&amp; op=
c2 !=3D 0)) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 r2-&gt;type |=3D ARM_CP_NO_MIGRATE;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r2-&gt;type |=3D ARM_CP_ALIAS;<br>
=C2=A0 =C2=A0 =C2=A0}<br>
<br>
=C2=A0 =C2=A0 =C2=A0/* Overriding of an existing definition must be explici=
tly<br>
<span class=3D"HOEnZb"><font color=3D"#888888">--<br>
1.9.1<br>
<br>
<br>
</font></span></blockquote></div><br></div><div class=3D"gmail_extra">It&#3=
9;s not always the case in the code, but wouldn&#39;t it also be true that =
any register marked ARM_CP_CONST should also be ARM_CP_RAW?</div><div class=
=3D"gmail_extra"><br></div></div>

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