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Fri, 08 Sep 2023 15:33:01 -0700 (PDT) MIME-Version: 1.0 References: <20230908033129.694-1-zhiwei_liu@linux.alibaba.com> In-Reply-To: <20230908033129.694-1-zhiwei_liu@linux.alibaba.com> From: Atish Patra Date: Fri, 8 Sep 2023 15:32:50 -0700 Message-ID: Subject: Re: [RESEND] qemu/timer: Add host ticks function for RISC-V To: LIU Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, LIU Zhiwei Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=atishp@atishpatra.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Sep 7, 2023 at 8:33=E2=80=AFPM LIU Zhiwei wrote: > > From: LIU Zhiwei > > Signed-off-by: LIU Zhiwei > --- > include/qemu/timer.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/include/qemu/timer.h b/include/qemu/timer.h > index 9a91cb1248..105767c195 100644 > --- a/include/qemu/timer.h > +++ b/include/qemu/timer.h > @@ -979,6 +979,25 @@ static inline int64_t cpu_get_host_ticks(void) > return cur - ofs; > } > > +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen =3D=3D 3= 2 > +static inline int64_t cpu_get_host_ticks(void) > +{ > + uint32_t lo, hi; > + asm volatile("RDCYCLE %0\n\t" > + "RDCYCLEH %1" > + : "=3Dr"(lo), "=3Dr"(hi)); > + return lo | (uint64_t)hi << 32; > +} > + > +#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen > 32 > +static inline int64_t cpu_get_host_ticks(void) > +{ > + int64_t val; > + > + asm volatile("RDCYCLE %0" : "=3Dr"(val)); > + return val; > +} > + rdcycle won't be accessible from the user space directly in the future. rdcycle will be accessible via perf similar to other architectures from the next kernel release [1]. rdtime must be used to compute the host ticks if the host is a riscv. This is the equivalent of rdtsc in x86. [1] https://lore.kernel.org/lkml/CAP-5=3DfVcMg7TL6W_jH61PW6dYMobuTs13d4JDuT= Ax=3DmxJ+PNtQ@mail.gmail.com/T/#md852c28f4070212973b796c232ecd37dc1c6cb2b > #else > /* The host CPU doesn't have an easily accessible cycle counter. > Just return a monotonically increasing value. This will be > -- > 2.17.1 > > --=20 Regards, Atish