* [PATCH v3 0/6] Privilege version update
@ 2022-02-06 9:18 Atish Patra
2022-02-06 9:18 ` [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering Atish Patra
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Atish Patra @ 2022-02-06 9:18 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Bin Meng, Atish Patra, Palmer Dabbelt,
qemu-riscv
RISC-V International (RVI) has ratified many RISC-V ISA extensions recently[1].
The privileged specification version is also upgraded to v1.12. It means
certain CSRs introduced in v1.12 should only be accessible only if the
priv specification version supported is equal or greater than v1.12.
Doing this check in predicate function is not scalable as there will be
new CSRs introduced in the future versions of the privileged specification.
This series tries to address this problem by adding a field in the csr_ops
which can be checked in csrrw function before invoking the predicate function.
To keep the code churn to minimum, it is assumed that the minimum version of
the privilege version supported for any CSR is v1.10 unless specified
explicitly in the csr_ops table. Any new CSRs introduced in v1.12 have been
updated accordingly.
This will work fine for any ratified extensions. However, it is bit unclear
what should be done for the stable draft extensions. My suggestion is not
to update the priv field in the CSR ops table until the extension is
marked experimental (i.e. not frozen/ratified). Once the extension is
ratified and graduated from experimental to available stage, the privileged
spec version should be updated in the csr table if required. I am open to
other suggestions as well.
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
This series is rebased on top of the AIA v8 to avoid conflicts.
Changes from v2->v3:
1. Only update the bits defined in *envcfg CSR
Changes from v1->v2:
1. Unified both [m/h]envcfg & [m/h]envcfgh into one.
2. Changed the priv spec version enumeration
3. Improved csr_ops table to provide better redability.
4. Fixed the compilation error for CONFIG_USER_ONLY
5. Rebased on top of the AIA series.
Atish Patra (6):
target/riscv: Define simpler privileged spec version numbering
target/riscv: Add the privileged spec version 1.12.0
target/riscv: Introduce privilege version field in the CSR ops.
target/riscv: Add support for mconfigptr
target/riscv: Add *envcfg* CSRs support
target/riscv: Enable privileged spec version 1.12
target/riscv/cpu.c | 8 +-
target/riscv/cpu.h | 15 ++-
target/riscv/cpu_bits.h | 40 ++++++++
target/riscv/csr.c | 217 +++++++++++++++++++++++++++++++++-------
target/riscv/machine.c | 24 +++++
5 files changed, 264 insertions(+), 40 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering 2022-02-06 9:18 [PATCH v3 0/6] Privilege version update Atish Patra @ 2022-02-06 9:18 ` Atish Patra 2022-02-21 21:37 ` Alistair Francis 2022-02-06 9:18 ` [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0 Atish Patra ` (4 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Atish Patra @ 2022-02-06 9:18 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Atish Patra, Bin Meng, Richard Henderson, Alistair Francis, Palmer Dabbelt Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9d24d678e98a..e5ff4c134c86 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,8 +82,11 @@ enum { RISCV_FEATURE_AIA }; -#define PRIV_VERSION_1_10_0 0x00011000 -#define PRIV_VERSION_1_11_0 0x00011100 +/* Privileged specification version */ +enum { + PRIV_VERSION_1_10_0 = 0, + PRIV_VERSION_1_11_0, +}; #define VEXT_VERSION_1_00_0 0x00010000 -- 2.30.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering 2022-02-06 9:18 ` [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering Atish Patra @ 2022-02-21 21:37 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2022-02-21 21:37 UTC (permalink / raw) To: Atish Patra Cc: open list:RISC-V, Bin Meng, Richard Henderson, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt On Sun, Feb 6, 2022 at 7:26 PM Atish Patra <atishp@rivosinc.com> wrote: > > Currently, the privileged specification version are defined in > a complex manner for no benefit. > > Simplify it by changing it to a simple enum based on. > > Suggested-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 9d24d678e98a..e5ff4c134c86 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -82,8 +82,11 @@ enum { > RISCV_FEATURE_AIA > }; > > -#define PRIV_VERSION_1_10_0 0x00011000 > -#define PRIV_VERSION_1_11_0 0x00011100 > +/* Privileged specification version */ > +enum { > + PRIV_VERSION_1_10_0 = 0, > + PRIV_VERSION_1_11_0, > +}; > > #define VEXT_VERSION_1_00_0 0x00010000 > > -- > 2.30.2 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0 2022-02-06 9:18 [PATCH v3 0/6] Privilege version update Atish Patra 2022-02-06 9:18 ` [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering Atish Patra @ 2022-02-06 9:18 ` Atish Patra 2022-02-21 21:38 ` Alistair Francis 2022-02-06 9:18 ` [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops Atish Patra ` (3 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Atish Patra @ 2022-02-06 9:18 UTC (permalink / raw) To: qemu-devel Cc: Alistair Francis, Bin Meng, Atish Patra, Palmer Dabbelt, qemu-riscv Add the definition for ratified privileged specification version v1.12 Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5ff4c134c86..60b847141db2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,6 +86,7 @@ enum { enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, + PRIV_VERSION_1_12_0, }; #define VEXT_VERSION_1_00_0 0x00010000 -- 2.30.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0 2022-02-06 9:18 ` [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0 Atish Patra @ 2022-02-21 21:38 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2022-02-21 21:38 UTC (permalink / raw) To: Atish Patra Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V On Sun, Feb 6, 2022 at 7:37 PM Atish Patra <atishp@rivosinc.com> wrote: > > Add the definition for ratified privileged specification version v1.12 > > Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e5ff4c134c86..60b847141db2 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -86,6 +86,7 @@ enum { > enum { > PRIV_VERSION_1_10_0 = 0, > PRIV_VERSION_1_11_0, > + PRIV_VERSION_1_12_0, > }; > > #define VEXT_VERSION_1_00_0 0x00010000 > -- > 2.30.2 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops. 2022-02-06 9:18 [PATCH v3 0/6] Privilege version update Atish Patra 2022-02-06 9:18 ` [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering Atish Patra 2022-02-06 9:18 ` [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0 Atish Patra @ 2022-02-06 9:18 ` Atish Patra 2022-02-21 21:41 ` Alistair Francis 2022-02-06 9:18 ` [PATCH v3 4/6] target/riscv: Add support for mconfigptr Atish Patra ` (2 subsequent siblings) 5 siblings, 1 reply; 13+ messages in thread From: Atish Patra @ 2022-02-06 9:18 UTC (permalink / raw) To: qemu-devel Cc: Alistair Francis, Bin Meng, Atish Patra, Palmer Dabbelt, qemu-riscv To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60b847141db2..0741f9822cf0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -593,6 +593,8 @@ typedef struct { riscv_csr_op_fn op; riscv_csr_read128_fn read128; riscv_csr_write128_fn write128; + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ + uint32_t min_priv_ver; } riscv_csr_operations; /* CSR function table constants */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8c63caa39245..25a0df498669 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_FRM] = { "frm", fs, read_frm, write_frm }, [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, - [CSR_VL] = { "vl", vs, read_vl }, - [CSR_VTYPE] = { "vtype", vs, read_vtype }, - [CSR_VLENB] = { "vlenb", vs, read_vlenb }, + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VL] = { "vl", vs, read_vl, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VTYPE] = { "vtype", vs, read_vtype, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VLENB] = { "vlenb", vs, read_vlenb, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_instret }, [CSR_INSTRET] = { "instret", ctr, read_instret }, @@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, - [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg }, - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie }, - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, - [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL }, - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, - - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie }, - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, - - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, @@ -3154,7 +3186,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, /* Physical Memory Protection */ - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, + [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, -- 2.30.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops. 2022-02-06 9:18 ` [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops Atish Patra @ 2022-02-21 21:41 ` Alistair Francis 2022-02-22 20:37 ` Atish Patra 0 siblings, 1 reply; 13+ messages in thread From: Alistair Francis @ 2022-02-21 21:41 UTC (permalink / raw) To: Atish Patra Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V On Sun, Feb 6, 2022 at 7:19 PM Atish Patra <atishp@rivosinc.com> wrote: > > To allow/disallow the CSR access based on the privilege spec, a new field > in the csr_ops is introduced. It also adds the privileged specification > version (v1.12) for the CSRs introduced in the v1.12. This includes the > new ratified extensions such as Vector, Hypervisor and secconfig CSR. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> It might be worth mentioning that there is no enforcement in this commit Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 2 + > target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- > 2 files changed, 70 insertions(+), 35 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 60b847141db2..0741f9822cf0 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -593,6 +593,8 @@ typedef struct { > riscv_csr_op_fn op; > riscv_csr_read128_fn read128; > riscv_csr_write128_fn write128; > + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ > + uint32_t min_priv_ver; > } riscv_csr_operations; > > /* CSR function table constants */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 8c63caa39245..25a0df498669 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_FRM] = { "frm", fs, read_frm, write_frm }, > [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, > /* Vector CSRs */ > - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, > - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, > - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, > - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, > - [CSR_VL] = { "vl", vs, read_vl }, > - [CSR_VTYPE] = { "vtype", vs, read_vtype }, > - [CSR_VLENB] = { "vlenb", vs, read_vlenb }, > + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VL] = { "vl", vs, read_vl, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VTYPE] = { "vtype", vs, read_vtype, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VLENB] = { "vlenb", vs, read_vlenb, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > /* User Timers and Counters */ > [CSR_CYCLE] = { "cycle", ctr, read_instret }, > [CSR_INSTRET] = { "instret", ctr, read_instret }, > @@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, > [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, > > - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, > - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, > - [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg }, > - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, > - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, > - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie }, > - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, > - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, > - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, > - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, > - [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL }, > - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, > - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, > - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, > - > - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, > - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, > - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie }, > - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, > - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, > - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, > - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, > - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, > - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, > - > - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, > - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, > + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ > [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, > @@ -3154,7 +3186,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, > > /* Physical Memory Protection */ > - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, > + [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, > [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, > [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, > -- > 2.30.2 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops. 2022-02-21 21:41 ` Alistair Francis @ 2022-02-22 20:37 ` Atish Patra 0 siblings, 0 replies; 13+ messages in thread From: Atish Patra @ 2022-02-22 20:37 UTC (permalink / raw) To: Alistair Francis Cc: open list:RISC-V, Bin Meng, Atish Patra, qemu-devel@nongnu.org Developers, Palmer Dabbelt, Alistair Francis On Mon, Feb 21, 2022 at 1:42 PM Alistair Francis <alistair23@gmail.com> wrote: > > On Sun, Feb 6, 2022 at 7:19 PM Atish Patra <atishp@rivosinc.com> wrote: > > > > To allow/disallow the CSR access based on the privilege spec, a new field > > in the csr_ops is introduced. It also adds the privileged specification > > version (v1.12) for the CSRs introduced in the v1.12. This includes the > > new ratified extensions such as Vector, Hypervisor and secconfig CSR. > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > It might be worth mentioning that there is no enforcement in this commit > Sure. I will update the commit text and send a v4. > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > Alistair > > > --- > > target/riscv/cpu.h | 2 + > > target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- > > 2 files changed, 70 insertions(+), 35 deletions(-) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 60b847141db2..0741f9822cf0 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -593,6 +593,8 @@ typedef struct { > > riscv_csr_op_fn op; > > riscv_csr_read128_fn read128; > > riscv_csr_write128_fn write128; > > + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ > > + uint32_t min_priv_ver; > > } riscv_csr_operations; > > > > /* CSR function table constants */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 8c63caa39245..25a0df498669 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_FRM] = { "frm", fs, read_frm, write_frm }, > > [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, > > /* Vector CSRs */ > > - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, > > - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, > > - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, > > - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, > > - [CSR_VL] = { "vl", vs, read_vl }, > > - [CSR_VTYPE] = { "vtype", vs, read_vtype }, > > - [CSR_VLENB] = { "vlenb", vs, read_vlenb }, > > + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VL] = { "vl", vs, read_vl, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VTYPE] = { "vtype", vs, read_vtype, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VLENB] = { "vlenb", vs, read_vlenb, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > /* User Timers and Counters */ > > [CSR_CYCLE] = { "cycle", ctr, read_instret }, > > [CSR_INSTRET] = { "instret", ctr, read_instret }, > > @@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, > > [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, > > > > - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus }, > > - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg }, > > - [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg }, > > - [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip }, > > - [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip }, > > - [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie }, > > - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren }, > > - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie }, > > - [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval }, > > - [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst }, > > - [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL }, > > - [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp }, > > - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta }, > > - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah }, > > - > > - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus }, > > - [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip }, > > - [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie }, > > - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec }, > > - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch }, > > - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc }, > > - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause }, > > - [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval }, > > - [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp }, > > - > > - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 }, > > - [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, > > + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + > > + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + > > + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > > /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ > > [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, > > @@ -3154,7 +3186,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, > > > > /* Physical Memory Protection */ > > - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg }, > > + [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, > > [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, > > [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, > > -- > > 2.30.2 > > > > > -- Regards, Atish ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 4/6] target/riscv: Add support for mconfigptr 2022-02-06 9:18 [PATCH v3 0/6] Privilege version update Atish Patra ` (2 preceding siblings ...) 2022-02-06 9:18 ` [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops Atish Patra @ 2022-02-06 9:18 ` Atish Patra 2022-02-21 21:41 ` Alistair Francis 2022-02-06 9:18 ` [PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support Atish Patra 2022-02-06 9:18 ` [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12 Atish Patra 5 siblings, 1 reply; 13+ messages in thread From: Atish Patra @ 2022-02-06 9:18 UTC (permalink / raw) To: qemu-devel Cc: Alistair Francis, Bin Meng, Atish Patra, Palmer Dabbelt, qemu-riscv RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f96d26399607..89440241632a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -148,6 +148,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 /* Machine Trap Setup */ #define CSR_MSTATUS 0x300 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 25a0df498669..18fe17b62f51 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3021,6 +3021,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIMPID] = { "mimpid", any, read_zero }, [CSR_MHARTID] = { "mhartid", any, read_mhartid }, + [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, + .min_priv_ver = PRIV_VERSION_1_12_0 }, /* Machine Trap Setup */ [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, read_mstatus_i128 }, -- 2.30.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 4/6] target/riscv: Add support for mconfigptr 2022-02-06 9:18 ` [PATCH v3 4/6] target/riscv: Add support for mconfigptr Atish Patra @ 2022-02-21 21:41 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2022-02-21 21:41 UTC (permalink / raw) To: Atish Patra Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V On Sun, Feb 6, 2022 at 7:43 PM Atish Patra <atishp@rivosinc.com> wrote: > > RISC-V privileged specification v1.12 introduced a mconfigptr > which will hold the physical address of a configuration data > structure. As Qemu doesn't have a configuration data structure, > is read as zero which is valid as per the priv spec. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/csr.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index f96d26399607..89440241632a 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -148,6 +148,7 @@ > #define CSR_MARCHID 0xf12 > #define CSR_MIMPID 0xf13 > #define CSR_MHARTID 0xf14 > +#define CSR_MCONFIGPTR 0xf15 > > /* Machine Trap Setup */ > #define CSR_MSTATUS 0x300 > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 25a0df498669..18fe17b62f51 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3021,6 +3021,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MIMPID] = { "mimpid", any, read_zero }, > [CSR_MHARTID] = { "mhartid", any, read_mhartid }, > > + [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > /* Machine Trap Setup */ > [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, > read_mstatus_i128 }, > -- > 2.30.2 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support 2022-02-06 9:18 [PATCH v3 0/6] Privilege version update Atish Patra ` (3 preceding siblings ...) 2022-02-06 9:18 ` [PATCH v3 4/6] target/riscv: Add support for mconfigptr Atish Patra @ 2022-02-06 9:18 ` Atish Patra 2022-02-06 9:18 ` [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12 Atish Patra 5 siblings, 0 replies; 13+ messages in thread From: Atish Patra @ 2022-02-06 9:18 UTC (permalink / raw) To: qemu-devel Cc: Alistair Francis, Bin Meng, Atish Patra, Palmer Dabbelt, qemu-riscv The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 39 +++++++++++++++ target/riscv/csr.c | 107 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 24 +++++++++ 4 files changed, 175 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0741f9822cf0..e5c8694cf081 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -303,6 +303,11 @@ struct CPURISCVState { target_ulong spmbase; target_ulong upmmask; target_ulong upmbase; + + /* CSRs for execution enviornment configuration */ + uint64_t menvcfg; + target_ulong senvcfg; + uint64_t henvcfg; #endif float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 89440241632a..58a0a8d69f72 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -202,6 +202,9 @@ #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +/* Supervisor Configuration CSRs */ +#define CSR_SENVCFG 0x10A + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -247,6 +250,10 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 +/* Hypervisor Configuration CSRs */ +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -290,6 +297,10 @@ #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 +/* Machine Configuration CSRs */ +#define CSR_MENVCFG 0x30A +#define CSR_MENVCFGH 0x31A + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -654,6 +665,34 @@ typedef enum RISCVException { #define PM_EXT_CLEAN 0x00000002ULL #define PM_EXT_DIRTY 0x00000003ULL +/* Execution enviornment configuration bits */ +#define MENVCFG_FIOM BIT(0) +#define MENVCFG_CBIE (3UL << 4) +#define MENVCFG_CBCFE BIT(6) +#define MENVCFG_CBZE BIT(7) +#define MENVCFG_PBMTE BIT(62) +#define MENVCFG_STCE BIT(63) + +/* For RV32 */ +#define MENVCFGH_PBMTE BIT(30) +#define MENVCFGH_STCE BIT(31) + +#define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_CBIE MENVCFG_CBIE +#define SENVCFG_CBCFE MENVCFG_CBCFE +#define SENVCFG_CBZE MENVCFG_CBZE + +#define HENVCFG_FIOM MENVCFG_FIOM +#define HENVCFG_CBIE MENVCFG_CBIE +#define HENVCFG_CBCFE MENVCFG_CBCFE +#define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PBMTE MENVCFG_PBMTE +#define HENVCFG_STCE MENVCFG_STCE + +/* For RV32 */ +#define HENVCFGH_PBMTE MENVCFGH_PBMTE +#define HENVCFGH_STCE MENVCFGH_STCE + /* Offsets for every pair of control bits per each priv level */ #define XS_OFFSET 0ULL #define U_OFFSET 2ULL diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 18fe17b62f51..ff7e36596447 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1366,6 +1366,101 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +/* Execution environment configuration setup */ +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; + + if (riscv_cpu_mxl(env) == MXL_RV64) { + mask |= MENVCFG_PBMTE | MENVCFG_STCE; + } + env->menvcfg = (env->menvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->menvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; + uint64_t valh = (uint64_t)val << 32; + + env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->senvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; + + env->senvcfg = (env->senvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + + if (riscv_cpu_mxl(env) == MXL_RV64) { + mask |= HENVCFG_PBMTE | HENVCFG_STCE; + } + + env->henvcfg = (env->henvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->henvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; + uint64_t valh = (uint64_t)val << 32; + + env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3069,6 +3164,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, + /* Execution environment configuration */ + [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 9895930b2976..4a50a05937fa 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -220,6 +220,29 @@ static const VMStateDescription vmstate_kvmtimer = { } }; +/* TODO: henvcfg need both hyper_needed & envcfg_needed */ +static bool envcfg_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0); +} + +static const VMStateDescription vmstate_envcfg = { + .name = "cpu/envcfg", + .version_id = 1, + .minimum_version_id = 1, + .needed = envcfg_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.menvcfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINT64(env.henvcfg, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 3, @@ -280,6 +303,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_pointermasking, &vmstate_rv128, &vmstate_kvmtimer, + &vmstate_envcfg, NULL } }; -- 2.30.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12 2022-02-06 9:18 [PATCH v3 0/6] Privilege version update Atish Patra ` (4 preceding siblings ...) 2022-02-06 9:18 ` [PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support Atish Patra @ 2022-02-06 9:18 ` Atish Patra 2022-02-21 21:40 ` Alistair Francis 5 siblings, 1 reply; 13+ messages in thread From: Atish Patra @ 2022-02-06 9:18 UTC (permalink / raw) To: qemu-devel Cc: Alistair Francis, Bin Meng, Atish Patra, Palmer Dabbelt, qemu-riscv Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.c | 8 +++++--- target/riscv/csr.c | 5 +++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2668f9c358b2..1c72dfffdc61 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } #if defined(TARGET_RISCV64) @@ -474,7 +474,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version = PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { priv_version = PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version = PRIV_VERSION_1_10_0; @@ -489,7 +491,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (priv_version) { set_priv_version(env, priv_version); } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } if (cpu->cfg.mmu) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ff7e36596447..1c70c19cf9bd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2886,6 +2886,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ int read_only = get_field(csrno, 0xC00) == 3; + int csr_min_priv = csr_ops[csrno].min_priv_ver; #if !defined(CONFIG_USER_ONLY) int effective_priv = env->priv; @@ -2918,6 +2919,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, return RISCV_EXCP_ILLEGAL_INST; } + if (env->priv_ver < csr_min_priv) { + return RISCV_EXCP_ILLEGAL_INST; + } + return csr_ops[csrno].predicate(env, csrno); } -- 2.30.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12 2022-02-06 9:18 ` [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12 Atish Patra @ 2022-02-21 21:40 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2022-02-21 21:40 UTC (permalink / raw) To: Atish Patra Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V On Sun, Feb 6, 2022 at 7:51 PM Atish Patra <atishp@rivosinc.com> wrote: > > Virt machine uses privileged specification version 1.12 now. > All other machine continue to use the default one defined for that > machine unless changed to 1.12 by the user explicitly. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 8 +++++--- > target/riscv/csr.c | 5 +++++ > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 2668f9c358b2..1c72dfffdc61 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj) > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > #endif > - set_priv_version(env, PRIV_VERSION_1_11_0); > + set_priv_version(env, PRIV_VERSION_1_12_0); > } > > #if defined(TARGET_RISCV64) > @@ -474,7 +474,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > > if (cpu->cfg.priv_spec) { > - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { > + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { > + priv_version = PRIV_VERSION_1_12_0; > + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { > priv_version = PRIV_VERSION_1_11_0; > } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { > priv_version = PRIV_VERSION_1_10_0; > @@ -489,7 +491,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (priv_version) { > set_priv_version(env, priv_version); > } else if (!env->priv_ver) { > - set_priv_version(env, PRIV_VERSION_1_11_0); > + set_priv_version(env, PRIV_VERSION_1_12_0); > } > > if (cpu->cfg.mmu) { > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index ff7e36596447..1c70c19cf9bd 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2886,6 +2886,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, > { > /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ > int read_only = get_field(csrno, 0xC00) == 3; > + int csr_min_priv = csr_ops[csrno].min_priv_ver; > #if !defined(CONFIG_USER_ONLY) > int effective_priv = env->priv; > > @@ -2918,6 +2919,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, > return RISCV_EXCP_ILLEGAL_INST; > } > > + if (env->priv_ver < csr_min_priv) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > return csr_ops[csrno].predicate(env, csrno); > } > > -- > 2.30.2 > > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-02-22 20:46 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-02-06 9:18 [PATCH v3 0/6] Privilege version update Atish Patra 2022-02-06 9:18 ` [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering Atish Patra 2022-02-21 21:37 ` Alistair Francis 2022-02-06 9:18 ` [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0 Atish Patra 2022-02-21 21:38 ` Alistair Francis 2022-02-06 9:18 ` [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops Atish Patra 2022-02-21 21:41 ` Alistair Francis 2022-02-22 20:37 ` Atish Patra 2022-02-06 9:18 ` [PATCH v3 4/6] target/riscv: Add support for mconfigptr Atish Patra 2022-02-21 21:41 ` Alistair Francis 2022-02-06 9:18 ` [PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support Atish Patra 2022-02-06 9:18 ` [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12 Atish Patra 2022-02-21 21:40 ` Alistair Francis
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