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To: Jason Chien Cc: Rajnesh Kanwal , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, tech-control-transfer-records@lists.riscv.org Content-Type: multipart/alternative; boundary="000000000000353ec8061a14e0d0" Received-SPF: pass client-ip=2607:f8b0:4864:20::112d; envelope-from=beeman@rivosinc.com; helo=mail-yw1-x112d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 04 Jun 2024 15:54:07 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000353ec8061a14e0d0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jun 4, 2024 at 10:19=E2=80=AFAM Jason Chien wrote: > > Rajnesh Kanwal =E6=96=BC 2024/5/30 =E4=B8=8A=E5=8D=88 12:09 =E5=AF=AB=E9= =81=93: > > CTR extension adds a new instruction sctrclr to quickly > > clear the recorded entries buffer. > > > > Signed-off-by: Rajnesh Kanwal > > --- > > target/riscv/cpu.h | 1 + > > target/riscv/cpu_helper.c | 7 +++++++ > > target/riscv/insn32.decode | 1 + > > target/riscv/insn_trans/trans_privileged.c.inc | 10 ++++++++++ > > target/riscv/op_helper.c | 5 +++++ > > 5 files changed, 24 insertions(+) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index a294a5372a..fade71aa09 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -572,6 +572,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, > target_ulong newpriv, bool virt_en); > > void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask); > > void riscv_ctr_add_entry(CPURISCVState *env, target_long src, > target_long dst, > > uint64_t type, target_ulong prev_priv, bool > prev_virt); > > +void riscv_ctr_clear(CPURISCVState *env); > > > > void riscv_translate_init(void); > > G_NORETURN void riscv_raise_exception(CPURISCVState *env, > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index e064a7306e..45502f50a7 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -704,6 +704,13 @@ void riscv_ctr_freeze(CPURISCVState *env, uint64_t > freeze_mask) > > } > > } > > > > +void riscv_ctr_clear(CPURISCVState *env) > > +{ > > + memset(env->ctr_src, 0x0, sizeof(env->ctr_src)); > > + memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst)); > > + memset(env->ctr_data, 0x0, sizeof(env->ctr_data)); > > +} > > + > > static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt) > > { > > switch (priv) { > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > > index 9cb1a1b4ec..d3d38c7c68 100644 > > --- a/target/riscv/insn32.decode > > +++ b/target/riscv/insn32.decode > > @@ -107,6 +107,7 @@ > > # *** Privileged Instructions *** > > ecall 000000000000 00000 000 00000 1110011 > > ebreak 000000000001 00000 000 00000 1110011 > > +sctrclr 000100000100 00000 000 00000 1110011 > > uret 0000000 00010 00000 000 00000 1110011 > > sret 0001000 00010 00000 000 00000 1110011 > > mret 0011000 00010 00000 000 00000 1110011 > > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc > b/target/riscv/insn_trans/trans_privileged.c.inc > > index 339d659151..dd9da8651f 100644 > > --- a/target/riscv/insn_trans/trans_privileged.c.inc > > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > > @@ -69,6 +69,16 @@ static bool trans_ebreak(DisasContext *ctx, > arg_ebreak *a) > > return true; > > } > > > > +static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a) > > +{ > > +#ifndef CONFIG_USER_ONLY > If both of smctr and ssctr are not enabled, it is an illegal instruction. > > + gen_helper_ctr_clear(tcg_env); > > + return true; > > +#else > > + return false; > > +#endif > > +} > > + > > static bool trans_uret(DisasContext *ctx, arg_uret *a) > > { > > return false; > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > > index c8053d9c2f..89423c04b3 100644 > > --- a/target/riscv/op_helper.c > > +++ b/target/riscv/op_helper.c > > @@ -461,6 +461,11 @@ void helper_ctr_branch(CPURISCVState *env, > target_ulong src, target_ulong dest, > > } > > } > > > > +void helper_ctr_clear(CPURISCVState *env) > > +{ > > There should be some checks here. > The spec states: > SCTRCLR raises an illegal-instruction exception in U-mode, and a > virtual-instruction exception in VU-mode, unless CTR state enable access > restrictions apply. > > I don't quite understand "unless CTR state enable access restrictions > apply" though. > The next sentence says "See Chapter 5", which states that execution of SCTRCLR raises an illegal instruction exception if mstateen0.CTR=3D0 and th= e priv mode is not M-mode, and it raises a virtual instruction exception if mstateen0.CTR=3D0 && hstateen0.CTR=3D1 and the priv mode is VS-mode. > > > + riscv_ctr_clear(env); > > +} > > + > > void helper_wfi(CPURISCVState *env) > > { > > CPUState *cs =3D env_cpu(env); > --000000000000353ec8061a14e0d0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Tue, Jun 4, 2024 at 10:19=E2=80=AF= AM Jason Chien <jason.chien@si= five.com> wrote:

Rajnesh Kanwal =E6=96=BC 2024/5/30 =E4=B8=8A=E5=8D=88 12:09 =E5=AF=AB=E9=81= =93:
> CTR extension adds a new instruction sctrclr to quickly
> clear the recorded entries buffer.
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> ---
>=C2=A0 =C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1= +
>=C2=A0 =C2=A0target/riscv/cpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 7 +++++++
>=C2=A0 =C2=A0target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
>=C2=A0 =C2=A0target/riscv/insn_trans/trans_privileged.c.inc | 10 ++++++= ++++
>=C2=A0 =C2=A0target/riscv/op_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 5 +++++
>=C2=A0 =C2=A05 files changed, 24 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a294a5372a..fade71aa09 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -572,6 +572,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target= _ulong newpriv, bool virt_en);
>=C2=A0 =C2=A0void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_= mask);
>=C2=A0 =C2=A0void riscv_ctr_add_entry(CPURISCVState *env, target_long s= rc, target_long dst,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t type, target_ulong prev_priv, bool pre= v_virt);
> +void riscv_ctr_clear(CPURISCVState *env);
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0void riscv_translate_init(void);
>=C2=A0 =C2=A0G_NORETURN void riscv_raise_exception(CPURISCVState *env,<= br> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e064a7306e..45502f50a7 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -704,6 +704,13 @@ void riscv_ctr_freeze(CPURISCVState *env, uint64_= t freeze_mask)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +void riscv_ctr_clear(CPURISCVState *env)
> +{
> +=C2=A0 =C2=A0 memset(env->ctr_src, 0x0, sizeof(env->ctr_src));<= br> > +=C2=A0 =C2=A0 memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst));<= br> > +=C2=A0 =C2=A0 memset(env->ctr_data, 0x0, sizeof(env->ctr_data))= ;
> +}
> +
>=C2=A0 =C2=A0static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, = bool virt)
>=C2=A0 =C2=A0{
>=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (priv) {
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 9cb1a1b4ec..d3d38c7c68 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -107,6 +107,7 @@
>=C2=A0 =C2=A0# *** Privileged Instructions ***
>=C2=A0 =C2=A0ecall=C2=A0 =C2=A0 =C2=A0 =C2=A0000000000000=C2=A0 =C2=A0 = =C2=A000000 000 00000 1110011
>=C2=A0 =C2=A0ebreak=C2=A0 =C2=A0 =C2=A0 000000000001=C2=A0 =C2=A0 =C2= =A000000 000 00000 1110011
> +sctrclr=C2=A0 =C2=A0 =C2=A0000100000100=C2=A0 =C2=A0 =C2=A000000 000 = 00000 1110011
>=C2=A0 =C2=A0uret=C2=A0 =C2=A0 =C2=A0 =C2=A0 0000000=C2=A0 =C2=A0 00010= 00000 000 00000 1110011
>=C2=A0 =C2=A0sret=C2=A0 =C2=A0 =C2=A0 =C2=A0 0001000=C2=A0 =C2=A0 00010= 00000 000 00000 1110011
>=C2=A0 =C2=A0mret=C2=A0 =C2=A0 =C2=A0 =C2=A0 0011000=C2=A0 =C2=A0 00010= 00000 000 00000 1110011
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/r= iscv/insn_trans/trans_privileged.c.inc
> index 339d659151..dd9da8651f 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -69,6 +69,16 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebr= eak *a)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return true;
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a)
> +{
> +#ifndef CONFIG_USER_ONLY
If both of smctr and ssctr are not enabled, it is an illegal instruction. > +=C2=A0 =C2=A0 gen_helper_ctr_clear(tcg_env);
> +=C2=A0 =C2=A0 return true;
> +#else
> +=C2=A0 =C2=A0 return false;
> +#endif
> +}
> +
>=C2=A0 =C2=A0static bool trans_uret(DisasContext *ctx, arg_uret *a)
>=C2=A0 =C2=A0{
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return false;
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index c8053d9c2f..89423c04b3 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -461,6 +461,11 @@ void helper_ctr_branch(CPURISCVState *env, target= _ulong src, target_ulong dest,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +void helper_ctr_clear(CPURISCVState *env)
> +{

There should be some checks here.
The spec states:
SCTRCLR raises an illegal-instruction exception in U-mode, and a
virtual-instruction exception in VU-mode, unless CTR state enable access restrictions apply.

I don't quite understand "unless CTR state enable access restricti= ons
apply" though.

The next sentence s= ays "See Chapter 5", which states that execution of SCTRCLR raise= s an illegal instruction exception if mstateen0.CTR=3D0 and the priv mode i= s not M-mode, and it raises a virtual instruction exception if mstateen0.CT= R=3D0 && hstateen0.CTR=3D1 and the priv mode is VS-mode.
= =C2=A0

> +=C2=A0 =C2=A0 riscv_ctr_clear(env);
> +}
> +
>=C2=A0 =C2=A0void helper_wfi(CPURISCVState *env)
>=C2=A0 =C2=A0{
>=C2=A0 =C2=A0 =C2=A0 =C2=A0CPUState *cs =3D env_cpu(env);
--000000000000353ec8061a14e0d0--