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To: Alistair Francis Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, MingZhu Yan Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b34; envelope-from=trdthg47@gmail.com; helo=mail-yb1-xb34.google.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, FREEMAIL_REPLY=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sorry about the email style, I'm not familiar with it yet > It's probably worth including this in the commit message. Agree, I'll do it. > It would be good to reference the sail implementation and the justification for the change there Sail implementation is probably here: https://github.com/riscv/sail-riscv/blob/master/model/riscv_platform.sail#L= 340 - related commit: https://github.com/riscv/sail-riscv/commit/848312ce7c59fa08c304cab4b4e8060c= 67d5dfc9 The following is the "infinite loop" part is exported by objdump from the test ELF of the add instruction generated from ACT ```txt 00000000800082a0 : 800082a0: 00001f17 auipc t5,0x1 800082a4: d61f2023 sw ra,-672(t5) # 80009000 800082a8: ff9ff06f j 800082a0 ``` QEMU cannot respond to the above `sw` behavior, It makes no distinction regarding the size written, I guess that currently qemu will only respond to the writing to the high 32 bits and low 32 bits of tohost twice in succession. I think the behavior here is very strange, and you can find aswaterman's description of HTIF(include RV32) at: https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment= -607657754 So this patch try to distinguish these cases based on size and addr. About the sail impl, there are some related discussions at: https://github.com/riscv/sail-riscv/issues/218 I made some summaries: - The implementation of sail as a workaround is not very ideal; we should follow the experience of spike I checked the impl of spike. Although spike handles tohost in a syscall manner, I don't think this means that spike is better. Compared to sail, it does not distinguish whether the write to tohost is 4 bytes or 8 bytes, but at least in act, it always works properly. - spike code: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/fesvr/htif.= cc#L265 - HTIF has been deprecated I don't know if this is true or not, because I haven't found any official comment. However, since ACT is still using htif and is not expected to change for quite a long time, and no new solutions have emerged, we should go ahead and implement it - What are the advantages of QEMU supporting ACT - do cross validation with sail/spike, and contributors can use ACT to verify the correctness when adding new instructions to QEMU. (we do have this need.) > If you think that the benefits of supporting ACT are not obvious, then I think we can remove all the code related to supporting ACT (should be the commit mentioned above) What do you think about this? Thank you! Alistair Francis =E4=BA=8E2024=E5=B9=B410=E6=9C=8816= =E6=97=A5=E5=91=A8=E4=B8=89 13:27=E5=86=99=E9=81=93=EF=BC=9A > > On Mon, Oct 14, 2024 at 8:08=E2=80=AFPM =E9=98=8E=E6=98=8E=E9=93=B8 wrote: > > > > Thank you for your reply and I'm sorry that I didn't explain it clearly= . > > > > - ACT is an official riscv test suite to check the riscv support of the= DUT(device under test). > > It's probably worth including this in the commit message. > > > - Currently ACT support using [sail-riscv](https://github.com/riscv/sai= l-riscv)(default) or [spike](https://github.com/riscv-software-src/riscv-is= a-sim) > > - QEMU is not supported yet=EF=BC=8Cbut someone made a commit: [commit]= (https://github.com/qemu/qemu/commit/66247edc8b6fb36d6b905babcd795068ea989a= d5) > > > > But there are still problems, so I'm trying to fix it. After debugging,= I found that it's a htif problem, and the idea of fixing it is referenced = from the sail-riscv implementation > > It would be good to reference the sail implementation and the > justification for the change there > > Alistair > > > > > "Alistair Francis" <alistair23@gmail.com>=E5=86=99=E9=81=93=EF=BC= =9A > > > On Fri, Sep 27, 2024 at 11:26=E2=80=AFPM MingZhu Yan wrote: > > > > > > > > Applications sometimes only write the lower 32-bit payload by= tes, this is used > > > > in ACT tests. As a workaround, this refers to the solution of= sail-riscv. > > > > > > I'm not sure what ACT is, but this feels like a guest bug, not a Q= EMU issue. > > > > > > Alistair > > > > > > > if the payload is written a few times with the same value, we= process the whole > > > > htif command anyway. > > > > > > > > Signed-off-by: MingZhu Yan > > > > --- > > > > hw/char/riscv_htif.c | 35 +++++++++++++++++++---------------= - > > > > 1 file changed, 19 insertions(+), 16 deletions(-) > > > > > > > > diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c > > > > index 9bef60def1..d74cce3bef 100644 > > > > --- a/hw/char/riscv_htif.c > > > > +++ b/hw/char/riscv_htif.c > > > > @@ -65,16 +65,8 @@ void htif_symbol_callback(const char *st_n= ame, int st_info, uint64_t st_value, > > > > { > > > > if (strcmp("fromhost", st_name) =3D=3D 0) { > > > > fromhost_addr =3D st_value; > > > > - if (st_size !=3D 8) { > > > > - error_report("HTIF fromhost must be 8 bytes"); > > > > - exit(1); > > > > - } > > > > } else if (strcmp("tohost", st_name) =3D=3D 0) { > > > > tohost_addr =3D st_value; > > > > - if (st_size !=3D 8) { > > > > - error_report("HTIF tohost must be 8 bytes"); > > > > - exit(1); > > > > - } > > > > } else if (strcmp("begin_signature", st_name) =3D=3D 0) = { > > > > begin_sig_addr =3D st_value; > > > > } else if (strcmp("end_signature", st_name) =3D=3D 0) { > > > > @@ -290,18 +282,26 @@ static void htif_mm_write(void *opaque,= hwaddr addr, > > > > uint64_t value, unsigned size) > > > > { > > > > HTIFState *s =3D opaque; > > > > - if (addr =3D=3D TOHOST_OFFSET1) { > > > > - if (s->tohost =3D=3D 0x0) { > > > > - s->allow_tohost =3D 1; > > > > - s->tohost =3D value & 0xFFFFFFFF; > > > > + int htif_cmd_write =3D 0; > > > > + if (size =3D=3D 8 && addr =3D=3D TOHOST_OFFSET1)= { > > > > + htif_cmd_write =3D 1; > > > > + s->tohost =3D value; > > > > + htif_handle_tohost_write(s, s->tohost); > > > > + } else if (size =3D=3D 4 && addr =3D=3D TOHOST_O= FFSET1) { > > > > + if ((value) =3D=3D (s->tohost & 0xFFFF)) { > > > > + s->allow_tohost =3D s->allow_tohost + 1; > > > > } else { > > > > s->allow_tohost =3D 0; > > > > } > > > > - } else if (addr =3D=3D TOHOST_OFFSET2) { > > > > - if (s->allow_tohost) { > > > > - s->tohost |=3D value << 32; > > > > - htif_handle_tohost_write(s, s->tohost); > > > > + s->tohost =3D deposit64(s->tohost, 0, 32, valu= e); > > > > + } else if (size =3D=3D 4 && addr =3D=3D TOHOST_O= FFSET2) { > > > > + if ((value & 0xFF) =3D=3D (s->tohost & 0x= FF00)) { > > > > + s->allow_tohost =3D s->allow_tohost + 1; > > > > + } else { > > > > + s->allow_tohost =3D 1; > > > > } > > > > + htif_cmd_write =3D 1; > > > > + s->tohost =3D deposit64(s->tohost, 32, 32, val= ue); > > > > } else if (addr =3D=3D FROMHOST_OFFSET1) { > > > > s->fromhost_inprogress =3D 1; > > > > s->fromhost =3D value & 0xFFFFFFFF; > > > > @@ -312,6 +312,9 @@ static void htif_mm_write(void *opaque, h= waddr addr, > > > > qemu_log("Invalid htif write: address %016" PRIx64 "= \n", > > > > (uint64_t)addr); > > > > } > > > > + if ((s->tohost =3D=3D 1 && htif_cmd_write) ||= s->allow_tohost > 2) { > > > > + htif_handle_tohost_write(s, s->tohost); > > > > + } > > > > } > > > > > > > > static const MemoryRegionOps htif_mm_ops =3D { > > > > -- > > > > 2.34.1 > > > > > > > > > >