From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DE9EC33CB3 for ; Sat, 1 Feb 2020 19:22:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC38220679 for ; Sat, 1 Feb 2020 19:22:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="S8K/c/GA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC38220679 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyLn-0005Z4-TK for qemu-devel@archiver.kernel.org; Sat, 01 Feb 2020 14:22:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56258) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixyKi-0004ep-O6 for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:21:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixyKd-00056g-TY for qemu-devel@nongnu.org; Sat, 01 Feb 2020 14:21:32 -0500 Received: from mail-il1-x144.google.com ([2607:f8b0:4864:20::144]:38623) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ixyKd-00053p-IW; Sat, 01 Feb 2020 14:21:27 -0500 Received: by mail-il1-x144.google.com with SMTP id f5so9202102ilq.5; Sat, 01 Feb 2020 11:21:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hH2p9D4xhPpCls8dAJ/VDtlf5nHEPRw54/B5G58lVzc=; b=S8K/c/GAEYBDJ9JlROdXQOTTu6NIP+1/G1b8r4X/oYe3ZngkHa/dPe74WOcPCdrW1b f5bxLzrBhRXep/CHpKOq5KhBYsTpf7QyP8WbUfPR1XTnEnQhDNKzyyfCz3BvjYDYNVoq DLcynZanSzIV98+jdc4ZcP5aBEFDYrieAi/Ax1tpJkGv6DVwBn6JVyH1X0MncuriHzG/ oCW6thYUR8zaYxOZOpR3Ew839mYEAKRAi6qvsvvAnh+W1d66FndZ9ox4K3JycFWo+lLQ w5zHWsQSOVJuHfUqeXHGDm/QQ5HHghHC4Ey+kGqrDxklvs0lwo07QQtrT+JocUXMaY/u bhYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hH2p9D4xhPpCls8dAJ/VDtlf5nHEPRw54/B5G58lVzc=; b=d0QZJrMO4L+Aai0HMQ//Zk2PsiC/u5VV+pYwmsheL2V6gdoE//4cdgQKDegAJAsHWs FW1eT6+V+cz0eEJVn07vZVZyc9b63XN3sQMOLCc+QfngftH5UurKpPHtfUSATASdc3z+ 8TdDUeiUcrdo/TFaZrwWzrDdNtLzzHQXCTM/2737c9qEQQSXn0qHl20/TBT3TbLV9z30 QPVOhKLuoY/9VldGmtE7XQ0JTI0WbiJW/BHeaPyZTWQ5zkjPLPudmcDnndg2/H9FvDR5 e7b0Jg9vLUiueaxRcvtzAohZKmXv7b905L5s0AB1hYgaTpYjA406IQs9Iku898PZNWRI seAw== X-Gm-Message-State: APjAAAX+Af/0QHbEQ/8VNHR8RnGSRMFaktaseIeyCh4UfEX77fLW4OYZ hGxML9QRMi0OEOJXHbB/Q8JVHkDI/4Z6Pb3Hkb8= X-Google-Smtp-Source: APXvYqyuWMmQ4boWxdiL4mk+LRsz8dqO3ZP/kxrbSL6tbkiSxLl3plx5eRqWz3jWItUegfcJin4yHF8SPwmzGF5IY6A= X-Received: by 2002:a92:5f45:: with SMTP id t66mr15465985ilb.28.1580584886373; Sat, 01 Feb 2020 11:21:26 -0800 (PST) MIME-Version: 1.0 References: <20200119005102.3847-1-nieklinnenbank@gmail.com> <20200119005102.3847-2-nieklinnenbank@gmail.com> <4aca4ea1-fb06-c0bf-d636-e6b842380a15@redhat.com> In-Reply-To: <4aca4ea1-fb06-c0bf-d636-e6b842380a15@redhat.com> From: Niek Linnenbank Date: Sat, 1 Feb 2020 20:21:15 +0100 Message-ID: Subject: Re: [PATCH v4 01/20] hw/arm: add Allwinner H3 System-on-Chip To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000b093a4059d889857" X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::144 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , jasowang@redhat.com, QEMU Developers , Beniamino Galvani , qemu-arm , imammedo@redhat.com, =?UTF-8?B?QWxleCBCZW5uw6ll?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000b093a4059d889857 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Philippe, I just got back from traveling and will start processing these and the other comments soon. On Sun, Jan 19, 2020 at 7:01 PM Philippe Mathieu-Daud=C3=A9 wrote: > On 1/19/20 1:50 AM, Niek Linnenbank wrote: > > The Allwinner H3 is a System on Chip containing four ARM Cortex A7 > > processor cores. Features and specifications include DDR2/DDR3 memory, > > SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and > > various I/O modules. This commit adds support for the Allwinner H3 > > System on Chip. > > > > Signed-off-by: Niek Linnenbank > > --- > > default-configs/arm-softmmu.mak | 1 + > > include/hw/arm/allwinner-h3.h | 106 +++++++++++ > > hw/arm/allwinner-h3.c | 327 +++++++++++++++++++++++++++++++= + > > MAINTAINERS | 7 + > > hw/arm/Kconfig | 8 + > > hw/arm/Makefile.objs | 1 + > > 6 files changed, 450 insertions(+) > > create mode 100644 include/hw/arm/allwinner-h3.h > > create mode 100644 hw/arm/allwinner-h3.c > > > > diff --git a/default-configs/arm-softmmu.mak > b/default-configs/arm-softmmu.mak > > index 645e6201bb..36a0e89daa 100644 > > --- a/default-configs/arm-softmmu.mak > > +++ b/default-configs/arm-softmmu.mak > > @@ -41,3 +41,4 @@ CONFIG_FSL_IMX25=3Dy > > CONFIG_FSL_IMX7=3Dy > > CONFIG_FSL_IMX6UL=3Dy > > CONFIG_SEMIHOSTING=3Dy > > +CONFIG_ALLWINNER_H3=3Dy > > diff --git a/include/hw/arm/allwinner-h3.h > b/include/hw/arm/allwinner-h3.h > > new file mode 100644 > > index 0000000000..2aac9b78ec > > --- /dev/null > > +++ b/include/hw/arm/allwinner-h3.h > > @@ -0,0 +1,106 @@ > > +/* > > + * Allwinner H3 System on Chip emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +/* > > + * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 > > + * processor cores. Features and specifications include DDR2/DDR3 > memory, > > + * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and > > + * various I/O modules. > > + * > > + * This implementation is based on the following datasheet: > > + * > > + * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf > > + * > > + * The latest datasheet and more info can be found on the Linux Sunxi > wiki: > > + * > > + * https://linux-sunxi.org/H3 > > + */ > > + > > +#ifndef HW_ARM_ALLWINNER_H3_H > > +#define HW_ARM_ALLWINNER_H3_H > > + > > +#include "qom/object.h" > > +#include "hw/arm/boot.h" > > +#include "hw/timer/allwinner-a10-pit.h" > > +#include "hw/intc/arm_gic.h" > > +#include "target/arm/cpu.h" > > + > > +/** > > + * Allwinner H3 device list > > + * > > + * This enumeration is can be used refer to a particular device in the > > + * Allwinner H3 SoC. For example, the physical memory base address for > > + * each device can be found in the AwH3State object in the memmap memb= er > > + * using the device enum value as index. > > + * > > + * @see AwH3State > > + */ > > +enum { > > + AW_H3_SRAM_A1, > > + AW_H3_SRAM_A2, > > + AW_H3_SRAM_C, > > + AW_H3_PIT, > > + AW_H3_UART0, > > + AW_H3_UART1, > > + AW_H3_UART2, > > + AW_H3_UART3, > > + AW_H3_GIC_DIST, > > + AW_H3_GIC_CPU, > > + AW_H3_GIC_HYP, > > + AW_H3_GIC_VCPU, > > + AW_H3_SDRAM > > +}; > > + > > +/** Total number of CPU cores in the H3 SoC */ > > +#define AW_H3_NUM_CPUS (4) > > + > > +/** > > + * Allwinner H3 object model > > + * @{ > > + */ > > + > > +/** Object type for the Allwinner H3 SoC */ > > +#define TYPE_AW_H3 "allwinner-h3" > > + > > +/** Convert input object to Allwinner H3 state object */ > > +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) > > + > > +/** @} */ > > + > > +/** > > + * Allwinner H3 object > > + * > > + * This struct contains the state of all the devices > > + * which are currently emulated by the H3 SoC code. > > + */ > > +typedef struct AwH3State { > > + /*< private >*/ > > + DeviceState parent_obj; > > + /*< public >*/ > > + > > + ARMCPU cpus[AW_H3_NUM_CPUS]; > > + const hwaddr *memmap; > > + AwA10PITState timer; > > + GICState gic; > > + MemoryRegion sram_a1; > > + MemoryRegion sram_a2; > > + MemoryRegion sram_c; > > +} AwH3State; > > + > > +#endif /* HW_ARM_ALLWINNER_H3_H */ > > diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c > > new file mode 100644 > > index 0000000000..efe6042af3 > > --- /dev/null > > +++ b/hw/arm/allwinner-h3.c > > @@ -0,0 +1,327 @@ > > +/* > > + * Allwinner H3 System on Chip emulation > > + * > > + * Copyright (C) 2019 Niek Linnenbank > > + * > > + * This program is free software: you can redistribute it and/or modif= y > > + * it under the terms of the GNU General Public License as published b= y > > + * the Free Software Foundation, either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see >. > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "exec/address-spaces.h" > > +#include "qapi/error.h" > > +#include "qemu/error-report.h" > > +#include "qemu/module.h" > > +#include "qemu/units.h" > > +#include "hw/qdev-core.h" > > +#include "cpu.h" > > +#include "hw/sysbus.h" > > +#include "hw/char/serial.h" > > +#include "hw/misc/unimp.h" > > +#include "sysemu/sysemu.h" > > +#include "hw/arm/allwinner-h3.h" > > + > > +/* Memory map */ > > +const hwaddr allwinner_h3_memmap[] =3D { > > + [AW_H3_SRAM_A1] =3D 0x00000000, > > + [AW_H3_SRAM_A2] =3D 0x00044000, > > + [AW_H3_SRAM_C] =3D 0x00010000, > > + [AW_H3_PIT] =3D 0x01c20c00, > > + [AW_H3_UART0] =3D 0x01c28000, > > + [AW_H3_UART1] =3D 0x01c28400, > > + [AW_H3_UART2] =3D 0x01c28800, > > + [AW_H3_UART3] =3D 0x01c28c00, > > + [AW_H3_GIC_DIST] =3D 0x01c81000, > > + [AW_H3_GIC_CPU] =3D 0x01c82000, > > + [AW_H3_GIC_HYP] =3D 0x01c84000, > > + [AW_H3_GIC_VCPU] =3D 0x01c86000, > > + [AW_H3_SDRAM] =3D 0x40000000 > > +}; > > + > > +/* List of unimplemented devices */ > > +struct AwH3Unimplemented { > > + const char *device_name; > > + hwaddr base; > > + hwaddr size; > > +} unimplemented[] =3D { > > + { "d-engine", 0x01000000, 4 * MiB }, > > + { "d-inter", 0x01400000, 128 * KiB }, > > + { "syscon", 0x01c00000, 4 * KiB }, > > + { "dma", 0x01c02000, 4 * KiB }, > > + { "nfdc", 0x01c03000, 4 * KiB }, > > + { "ts", 0x01c06000, 4 * KiB }, > > + { "keymem", 0x01c0b000, 4 * KiB }, > > + { "lcd0", 0x01c0c000, 4 * KiB }, > > + { "lcd1", 0x01c0d000, 4 * KiB }, > > + { "ve", 0x01c0e000, 4 * KiB }, > > + { "mmc0", 0x01c0f000, 4 * KiB }, > > + { "mmc1", 0x01c10000, 4 * KiB }, > > + { "mmc2", 0x01c11000, 4 * KiB }, > > + { "sid", 0x01c14000, 1 * KiB }, > > + { "crypto", 0x01c15000, 4 * KiB }, > > + { "msgbox", 0x01c17000, 4 * KiB }, > > + { "spinlock", 0x01c18000, 4 * KiB }, > > + { "usb0-otg", 0x01c19000, 4 * KiB }, > > + { "usb0", 0x01c1a000, 4 * KiB }, > > + { "usb1", 0x01c1b000, 4 * KiB }, > > + { "usb2", 0x01c1c000, 4 * KiB }, > > + { "usb3", 0x01c1d000, 4 * KiB }, > > + { "smc", 0x01c1e000, 4 * KiB }, > > + { "ccu", 0x01c20000, 1 * KiB }, > > + { "pio", 0x01c20800, 1 * KiB }, > > + { "owa", 0x01c21000, 1 * KiB }, > > + { "pwm", 0x01c21400, 1 * KiB }, > > + { "keyadc", 0x01c21800, 1 * KiB }, > > + { "pcm0", 0x01c22000, 1 * KiB }, > > + { "pcm1", 0x01c22400, 1 * KiB }, > > + { "pcm2", 0x01c22800, 1 * KiB }, > > + { "audio", 0x01c22c00, 2 * KiB }, > > + { "smta", 0x01c23400, 1 * KiB }, > > + { "ths", 0x01c25000, 1 * KiB }, > > + { "uart0", 0x01c28000, 1 * KiB }, > > + { "uart1", 0x01c28400, 1 * KiB }, > > + { "uart2", 0x01c28800, 1 * KiB }, > > + { "uart3", 0x01c28c00, 1 * KiB }, > > + { "twi0", 0x01c2ac00, 1 * KiB }, > > + { "twi1", 0x01c2b000, 1 * KiB }, > > + { "twi2", 0x01c2b400, 1 * KiB }, > > + { "scr", 0x01c2c400, 1 * KiB }, > > + { "emac", 0x01c30000, 64 * KiB }, > > + { "gpu", 0x01c40000, 64 * KiB }, > > + { "hstmr", 0x01c60000, 4 * KiB }, > > + { "dramcom", 0x01c62000, 4 * KiB }, > > + { "dramctl0", 0x01c63000, 4 * KiB }, > > + { "dramphy0", 0x01c65000, 4 * KiB }, > > + { "spi0", 0x01c68000, 4 * KiB }, > > + { "spi1", 0x01c69000, 4 * KiB }, > > + { "csi", 0x01cb0000, 320 * KiB }, > > + { "tve", 0x01e00000, 64 * KiB }, > > + { "hdmi", 0x01ee0000, 128 * KiB }, > > + { "rtc", 0x01f00000, 1 * KiB }, > > + { "r_timer", 0x01f00800, 1 * KiB }, > > + { "r_intc", 0x01f00c00, 1 * KiB }, > > + { "r_wdog", 0x01f01000, 1 * KiB }, > > + { "r_prcm", 0x01f01400, 1 * KiB }, > > + { "r_twd", 0x01f01800, 1 * KiB }, > > + { "r_cpucfg", 0x01f01c00, 1 * KiB }, > > + { "r_cir-rx", 0x01f02000, 1 * KiB }, > > + { "r_twi", 0x01f02400, 1 * KiB }, > > + { "r_uart", 0x01f02800, 1 * KiB }, > > + { "r_pio", 0x01f02c00, 1 * KiB }, > > + { "r_pwm", 0x01f03800, 1 * KiB }, > > + { "core-dbg", 0x3f500000, 128 * KiB }, > > + { "tsgen-ro", 0x3f506000, 4 * KiB }, > > + { "tsgen-ctl", 0x3f507000, 4 * KiB }, > > + { "ddr-mem", 0x40000000, 2 * GiB }, > > + { "n-brom", 0xffff0000, 32 * KiB }, > > + { "s-brom", 0xffff0000, 64 * KiB } > > +}; > > + > > +/* Per Processor Interrupts */ > > +enum { > > + AW_H3_GIC_PPI_MAINT =3D 9, > > + AW_H3_GIC_PPI_HYPTIMER =3D 10, > > + AW_H3_GIC_PPI_VIRTTIMER =3D 11, > > + AW_H3_GIC_PPI_SECTIMER =3D 13, > > + AW_H3_GIC_PPI_PHYSTIMER =3D 14 > > +}; > > + > > +/* Shared Processor Interrupts */ > > +enum { > > + AW_H3_GIC_SPI_UART0 =3D 0, > > + AW_H3_GIC_SPI_UART1 =3D 1, > > + AW_H3_GIC_SPI_UART2 =3D 2, > > + AW_H3_GIC_SPI_UART3 =3D 3, > > + AW_H3_GIC_SPI_TIMER0 =3D 18, > > + AW_H3_GIC_SPI_TIMER1 =3D 19, > > +}; > > + > > +/* Allwinner H3 general constants */ > > +enum { > > + AW_H3_GIC_NUM_SPI =3D 128 > > +}; > > + > > +static void allwinner_h3_init(Object *obj) > > +{ > > + AwH3State *s =3D AW_H3(obj); > > + > > + s->memmap =3D allwinner_h3_memmap; > > + > > + for (int i =3D 0; i < AW_H3_NUM_CPUS; i++) { > > + object_initialize_child(obj, "cpu[*]", &s->cpus[i], > sizeof(s->cpus[i]), > > + ARM_CPU_TYPE_NAME("cortex-a7"), > > + &error_abort, NULL); > > + } > > + > > + sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), > > + TYPE_ARM_GIC); > > + > > + sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), > > + TYPE_AW_A10_PIT); > > + object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer), > > + "clk0-freq", &error_abort); > > + object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), > > + "clk1-freq", &error_abort); > > +} > > + > > +static void allwinner_h3_realize(DeviceState *dev, Error **errp) > > +{ > > + AwH3State *s =3D AW_H3(dev); > > + unsigned i; > > + > > + /* CPUs */ > > + for (i =3D 0; i < AW_H3_NUM_CPUS; i++) { > > + > > + /* Provide Power State Coordination Interface */ > > + qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit", > > + QEMU_PSCI_CONDUIT_HVC); > > + > > + /* Disable secondary CPUs */ > > + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", > > + i > 0); > > + > > + /* All exception levels required */ > > + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); > > + qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); > > + > > + /* Mark realized */ > > + qdev_init_nofail(DEVICE(&s->cpus[i])); > > + } > > + > > + /* Generic Interrupt Controller */ > > + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI= + > > + GIC_INTERNAL); > > + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); > > + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); > > + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", > false); > > + qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions"= , > true); > > + qdev_init_nofail(DEVICE(&s->gic)); > > + > > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, > s->memmap[AW_H3_GIC_DIST]); > > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, > s->memmap[AW_H3_GIC_CPU]); > > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, > s->memmap[AW_H3_GIC_HYP]); > > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, > s->memmap[AW_H3_GIC_VCPU]); > > + > > + /* > > + * Wire the outputs from each CPU's generic timer and the GICv3 > > + * maintenance interrupt signal to the appropriate GIC PPI inputs, > > + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's > inputs. > > + */ > > + for (i =3D 0; i < AW_H3_NUM_CPUS; i++) { > > + DeviceState *cpudev =3D DEVICE(&s->cpus[i]); > > + int ppibase =3D AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + > GIC_NR_SGIS; > > + int irq; > > + /* > > + * Mapping from the output timer irq lines from the CPU to the > > + * GIC PPI inputs used for this board. > > + */ > > + const int timer_irq[] =3D { > > + [GTIMER_PHYS] =3D AW_H3_GIC_PPI_PHYSTIMER, > > + [GTIMER_VIRT] =3D AW_H3_GIC_PPI_VIRTTIMER, > > + [GTIMER_HYP] =3D AW_H3_GIC_PPI_HYPTIMER, > > + [GTIMER_SEC] =3D AW_H3_GIC_PPI_SECTIMER, > > + }; > > + > > + /* Connect CPU timer outputs to GIC PPI inputs */ > > + for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { > > + qdev_connect_gpio_out(cpudev, irq, > > + qdev_get_gpio_in(DEVICE(&s->gic), > > + ppibase + > timer_irq[irq])); > > + } > > + > > + /* Connect GIC outputs to CPU interrupt inputs */ > > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, > > + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); > > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS= , > > + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); > > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * > AW_H3_NUM_CPUS), > > + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); > > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * > AW_H3_NUM_CPUS), > > + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); > > + > > + /* GIC maintenance signal */ > > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * > AW_H3_NUM_CPUS), > > + qdev_get_gpio_in(DEVICE(&s->gic), > > + ppibase + > AW_H3_GIC_PPI_MAINT)); > > + } > > + > > + /* Timer */ > > + qdev_init_nofail(DEVICE(&s->timer)); > > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]= ); > > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, > > + qdev_get_gpio_in(DEVICE(&s->gic), > AW_H3_GIC_SPI_TIMER0)); > > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, > > + qdev_get_gpio_in(DEVICE(&s->gic), > AW_H3_GIC_SPI_TIMER1)); > > + > > + /* SRAM */ > > + memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", > > + 64 * KiB, &error_abort); > > + memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", > > + 32 * KiB, &error_abort); > > + memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", > > + 44 * KiB, &error_abort); > > + memory_region_add_subregion(get_system_memory(), > s->memmap[AW_H3_SRAM_A1], > > + &s->sram_a1); > > + memory_region_add_subregion(get_system_memory(), > s->memmap[AW_H3_SRAM_A2], > > + &s->sram_a2); > > + memory_region_add_subregion(get_system_memory(), > s->memmap[AW_H3_SRAM_C], > > + &s->sram_c); > > + > > + /* UART0. For future clocktree API: All UARTS are connected to > APB2_CLK. */ > > + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, > > + qdev_get_gpio_in(DEVICE(&s->gic), > AW_H3_GIC_SPI_UART0), > > + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); > > + /* UART1 */ > > + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2, > > + qdev_get_gpio_in(DEVICE(&s->gic), > AW_H3_GIC_SPI_UART1), > > + 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN); > > + /* UART2 */ > > + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2, > > + qdev_get_gpio_in(DEVICE(&s->gic), > AW_H3_GIC_SPI_UART2), > > + 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN); > > + /* UART3 */ > > + serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2, > > + qdev_get_gpio_in(DEVICE(&s->gic), > AW_H3_GIC_SPI_UART3), > > + 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN); > > + > > + /* Unimplemented devices */ > > + for (i =3D 0; i < ARRAY_SIZE(unimplemented); i++) { > > + create_unimplemented_device(unimplemented[i].device_name, > > + unimplemented[i].base, > > + unimplemented[i].size); > > + } > > +} > > + > > +static void allwinner_h3_class_init(ObjectClass *oc, void *data) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(oc); > > + > > + dc->realize =3D allwinner_h3_realize; > > + /* Reason: uses serial_hds and nd_table */ > > Maybe use "serial_hd()". Also nd_table is not used yet. > Thanks, this comment was outdated indeed, I'll correct it. > > > + dc->user_creatable =3D false; > > +} > > + > > +static const TypeInfo allwinner_h3_type_info =3D { > > + .name =3D TYPE_AW_H3, > > + .parent =3D TYPE_DEVICE, > > + .instance_size =3D sizeof(AwH3State), > > + .instance_init =3D allwinner_h3_init, > > + .class_init =3D allwinner_h3_class_init, > > +}; > > + > > +static void allwinner_h3_register_types(void) > > +{ > > + type_register_static(&allwinner_h3_type_info); > > +} > > + > > +type_init(allwinner_h3_register_types) > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 55d3642e6c..225582704d 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -481,6 +481,13 @@ F: hw/*/allwinner* > > F: include/hw/*/allwinner* > > F: hw/arm/cubieboard.c > > > > +Allwinner-h3 > > +M: Niek Linnenbank > > +L: qemu-arm@nongnu.org > > +S: Maintained > > +F: hw/*/allwinner-h3* > > +F: include/hw/*/allwinner-h3* > > + > > ARM PrimeCell and CMSDK devices > > M: Peter Maydell > > L: qemu-arm@nongnu.org > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > > index 3d86691ae0..bb75c1de17 100644 > > --- a/hw/arm/Kconfig > > +++ b/hw/arm/Kconfig > > @@ -295,6 +295,14 @@ config ALLWINNER_A10 > > select SERIAL > > select UNIMP > > > > +config ALLWINNER_H3 > > + bool > > + select ALLWINNER_A10_PIT > > We should now rename this as ALLWINNER_PIT. > I see your point, now both SoCs are using the A10 specific PIT timer. Previously we agreed to do the generalization of that timer in a separate patch series. I think it makes sense to also do the rename of this item as part of that separate series. > > > + select SERIAL > > + select ARM_TIMER > > + select ARM_GIC > > + select UNIMP > > + > > config RASPI > > bool > > select FRAMEBUFFER > > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs > > index 336f6dd374..ae577e875f 100644 > > --- a/hw/arm/Makefile.objs > > +++ b/hw/arm/Makefile.objs > > @@ -35,6 +35,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o > > obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o > > obj-$(CONFIG_STRONGARM) +=3D strongarm.o > > obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o > > +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o > > obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o > > obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o > > obj-$(CONFIG_STM32F405_SOC) +=3D stm32f405_soc.o > > > > Patch very clean! > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Tested-by: Philippe Mathieu-Daud=C3=A9 > > Thanks for reviewing Philippe! Regards, Niek --=20 Niek Linnenbank --000000000000b093a4059d889857 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Philippe,

I just got = back from traveling and will start processing these and the other comments = soon.

On Sun, Jan 19, 2020 at 7:01 PM Philippe Mathieu-Daud= =C3=A9 <philmd@redhat.com> w= rote:
On 1/19/20= 1:50 AM, Niek Linnenbank wrote:
> The Allwinner H3 is a System on Chip containing four ARM Cortex A7
> processor cores. Features and specifications include DDR2/DDR3 memory,=
> SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
> various I/O modules. This commit adds support for the Allwinner H3
> System on Chip.
>
> Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
> ---
>=C2=A0 =C2=A0default-configs/arm-softmmu.mak |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A0include/hw/arm/allwinner-h3.h=C2=A0 =C2=A0| 106 ++++++++++= +
>=C2=A0 =C2=A0hw/arm/allwinner-h3.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 327 ++++++++++++++++++++++++++++++++
>=C2=A0 =C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A07 +
>=C2=A0 =C2=A0hw/arm/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A08 +
>=C2=A0 =C2=A0hw/arm/Makefile.objs=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 |=C2=A0 =C2=A01 +
>=C2=A0 =C2=A06 files changed, 450 insertions(+)
>=C2=A0 =C2=A0create mode 100644 include/hw/arm/allwinner-h3.h
>=C2=A0 =C2=A0create mode 100644 hw/arm/allwinner-h3.c
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-sof= tmmu.mak
> index 645e6201bb..36a0e89daa 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -41,3 +41,4 @@ CONFIG_FSL_IMX25=3Dy
>=C2=A0 =C2=A0CONFIG_FSL_IMX7=3Dy
>=C2=A0 =C2=A0CONFIG_FSL_IMX6UL=3Dy
>=C2=A0 =C2=A0CONFIG_SEMIHOSTING=3Dy
> +CONFIG_ALLWINNER_H3=3Dy
> diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-= h3.h
> new file mode 100644
> index 0000000000..2aac9b78ec
> --- /dev/null
> +++ b/include/hw/arm/allwinner-h3.h
> @@ -0,0 +1,106 @@
> +/*
> + * Allwinner H3 System on Chip emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +/*
> + * The Allwinner H3 is a System on Chip containing four ARM Cortex A7=
> + * processor cores. Features and specifications include DDR2/DDR3 mem= ory,
> + * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and<= br> > + * various I/O modules.
> + *
> + * This implementation is based on the following datasheet:
> + *
> + *=C2=A0 =C2=A0https://linux-sunxi= .org/File:Allwinner_H3_Datasheet_V1.2.pdf
> + *
> + * The latest datasheet and more info can be found on the Linux Sunxi= wiki:
> + *
> + *=C2=A0 =C2=A0https://linux-sunxi.org/H3
> + */
> +
> +#ifndef HW_ARM_ALLWINNER_H3_H
> +#define HW_ARM_ALLWINNER_H3_H
> +
> +#include "qom/object.h"
> +#include "hw/arm/boot.h"
> +#include "hw/timer/allwinner-a10-pit.h"
> +#include "hw/intc/arm_gic.h"
> +#include "target/arm/cpu.h"
> +
> +/**
> + * Allwinner H3 device list
> + *
> + * This enumeration is can be used refer to a particular device in th= e
> + * Allwinner H3 SoC. For example, the physical memory base address fo= r
> + * each device can be found in the AwH3State object in the memmap mem= ber
> + * using the device enum value as index.
> + *
> + * @see AwH3State
> + */
> +enum {
> +=C2=A0 =C2=A0 AW_H3_SRAM_A1,
> +=C2=A0 =C2=A0 AW_H3_SRAM_A2,
> +=C2=A0 =C2=A0 AW_H3_SRAM_C,
> +=C2=A0 =C2=A0 AW_H3_PIT,
> +=C2=A0 =C2=A0 AW_H3_UART0,
> +=C2=A0 =C2=A0 AW_H3_UART1,
> +=C2=A0 =C2=A0 AW_H3_UART2,
> +=C2=A0 =C2=A0 AW_H3_UART3,
> +=C2=A0 =C2=A0 AW_H3_GIC_DIST,
> +=C2=A0 =C2=A0 AW_H3_GIC_CPU,
> +=C2=A0 =C2=A0 AW_H3_GIC_HYP,
> +=C2=A0 =C2=A0 AW_H3_GIC_VCPU,
> +=C2=A0 =C2=A0 AW_H3_SDRAM
> +};
> +
> +/** Total number of CPU cores in the H3 SoC */
> +#define AW_H3_NUM_CPUS=C2=A0 =C2=A0 =C2=A0 (4)
> +
> +/**
> + * Allwinner H3 object model
> + * @{
> + */
> +
> +/** Object type for the Allwinner H3 SoC */
> +#define TYPE_AW_H3 "allwinner-h3"
> +
> +/** Convert input object to Allwinner H3 state object */
> +#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
> +
> +/** @} */
> +
> +/**
> + * Allwinner H3 object
> + *
> + * This struct contains the state of all the devices
> + * which are currently emulated by the H3 SoC code.
> + */
> +typedef struct AwH3State {
> +=C2=A0 =C2=A0 /*< private >*/
> +=C2=A0 =C2=A0 DeviceState parent_obj;
> +=C2=A0 =C2=A0 /*< public >*/
> +
> +=C2=A0 =C2=A0 ARMCPU cpus[AW_H3_NUM_CPUS];
> +=C2=A0 =C2=A0 const hwaddr *memmap;
> +=C2=A0 =C2=A0 AwA10PITState timer;
> +=C2=A0 =C2=A0 GICState gic;
> +=C2=A0 =C2=A0 MemoryRegion sram_a1;
> +=C2=A0 =C2=A0 MemoryRegion sram_a2;
> +=C2=A0 =C2=A0 MemoryRegion sram_c;
> +} AwH3State;
> +
> +#endif /* HW_ARM_ALLWINNER_H3_H */
> diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
> new file mode 100644
> index 0000000000..efe6042af3
> --- /dev/null
> +++ b/hw/arm/allwinner-h3.c
> @@ -0,0 +1,327 @@
> +/*
> + * Allwinner H3 System on Chip emulation
> + *
> + * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
> + *
> + * This program is free software: you can redistribute it and/or modi= fy
> + * it under the terms of the GNU General Public License as published = by
> + * the Free Software Foundation, either version 2 of the License, or<= br> > + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the=
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License<= br> > + * along with this program.=C2=A0 If not, see <http://www.gnu.o= rg/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "exec/address-spaces.h"
> +#include "qapi/error.h"
> +#include "qemu/error-report.h"
> +#include "qemu/module.h"
> +#include "qemu/units.h"
> +#include "hw/qdev-core.h"
> +#include "cpu.h"
> +#include "hw/sysbus.h"
> +#include "hw/char/serial.h"
> +#include "hw/misc/unimp.h"
> +#include "sysemu/sysemu.h"
> +#include "hw/arm/allwinner-h3.h"
> +
> +/* Memory map */
> +const hwaddr allwinner_h3_memmap[] =3D {
> +=C2=A0 =C2=A0 [AW_H3_SRAM_A1]=C2=A0 =C2=A0 =3D 0x00000000,
> +=C2=A0 =C2=A0 [AW_H3_SRAM_A2]=C2=A0 =C2=A0 =3D 0x00044000,
> +=C2=A0 =C2=A0 [AW_H3_SRAM_C]=C2=A0 =C2=A0 =C2=A0=3D 0x00010000,
> +=C2=A0 =C2=A0 [AW_H3_PIT]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x01c20c00,<= br> > +=C2=A0 =C2=A0 [AW_H3_UART0]=C2=A0 =C2=A0 =C2=A0 =3D 0x01c28000,
> +=C2=A0 =C2=A0 [AW_H3_UART1]=C2=A0 =C2=A0 =C2=A0 =3D 0x01c28400,
> +=C2=A0 =C2=A0 [AW_H3_UART2]=C2=A0 =C2=A0 =C2=A0 =3D 0x01c28800,
> +=C2=A0 =C2=A0 [AW_H3_UART3]=C2=A0 =C2=A0 =C2=A0 =3D 0x01c28c00,
> +=C2=A0 =C2=A0 [AW_H3_GIC_DIST]=C2=A0 =C2=A0=3D 0x01c81000,
> +=C2=A0 =C2=A0 [AW_H3_GIC_CPU]=C2=A0 =C2=A0 =3D 0x01c82000,
> +=C2=A0 =C2=A0 [AW_H3_GIC_HYP]=C2=A0 =C2=A0 =3D 0x01c84000,
> +=C2=A0 =C2=A0 [AW_H3_GIC_VCPU]=C2=A0 =C2=A0=3D 0x01c86000,
> +=C2=A0 =C2=A0 [AW_H3_SDRAM]=C2=A0 =C2=A0 =C2=A0 =3D 0x40000000
> +};
> +
> +/* List of unimplemented devices */
> +struct AwH3Unimplemented {
> +=C2=A0 =C2=A0 const char *device_name;
> +=C2=A0 =C2=A0 hwaddr base;
> +=C2=A0 =C2=A0 hwaddr size;
> +} unimplemented[] =3D {
> +=C2=A0 =C2=A0 { "d-engine",=C2=A0 0x01000000, 4 * MiB }, > +=C2=A0 =C2=A0 { "d-inter",=C2=A0 =C2=A00x01400000, 128 * Ki= B },
> +=C2=A0 =C2=A0 { "syscon",=C2=A0 =C2=A0 0x01c00000, 4 * KiB = },
> +=C2=A0 =C2=A0 { "dma",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c02000= , 4 * KiB },
> +=C2=A0 =C2=A0 { "nfdc",=C2=A0 =C2=A0 =C2=A0 0x01c03000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "ts",=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x01c06000= , 4 * KiB },
> +=C2=A0 =C2=A0 { "keymem",=C2=A0 =C2=A0 0x01c0b000, 4 * KiB = },
> +=C2=A0 =C2=A0 { "lcd0",=C2=A0 =C2=A0 =C2=A0 0x01c0c000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "lcd1",=C2=A0 =C2=A0 =C2=A0 0x01c0d000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "ve",=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x01c0e000= , 4 * KiB },
> +=C2=A0 =C2=A0 { "mmc0",=C2=A0 =C2=A0 =C2=A0 0x01c0f000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "mmc1",=C2=A0 =C2=A0 =C2=A0 0x01c10000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "mmc2",=C2=A0 =C2=A0 =C2=A0 0x01c11000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "sid",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c14000= , 1 * KiB },
> +=C2=A0 =C2=A0 { "crypto",=C2=A0 =C2=A0 0x01c15000, 4 * KiB = },
> +=C2=A0 =C2=A0 { "msgbox",=C2=A0 =C2=A0 0x01c17000, 4 * KiB = },
> +=C2=A0 =C2=A0 { "spinlock",=C2=A0 0x01c18000, 4 * KiB }, > +=C2=A0 =C2=A0 { "usb0-otg",=C2=A0 0x01c19000, 4 * KiB }, > +=C2=A0 =C2=A0 { "usb0",=C2=A0 =C2=A0 =C2=A0 0x01c1a000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "usb1",=C2=A0 =C2=A0 =C2=A0 0x01c1b000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "usb2",=C2=A0 =C2=A0 =C2=A0 0x01c1c000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "usb3",=C2=A0 =C2=A0 =C2=A0 0x01c1d000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "smc",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c1e000= , 4 * KiB },
> +=C2=A0 =C2=A0 { "ccu",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c20000= , 1 * KiB },
> +=C2=A0 =C2=A0 { "pio",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c20800= , 1 * KiB },
> +=C2=A0 =C2=A0 { "owa",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c21000= , 1 * KiB },
> +=C2=A0 =C2=A0 { "pwm",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c21400= , 1 * KiB },
> +=C2=A0 =C2=A0 { "keyadc",=C2=A0 =C2=A0 0x01c21800, 1 * KiB = },
> +=C2=A0 =C2=A0 { "pcm0",=C2=A0 =C2=A0 =C2=A0 0x01c22000, 1 *= KiB },
> +=C2=A0 =C2=A0 { "pcm1",=C2=A0 =C2=A0 =C2=A0 0x01c22400, 1 *= KiB },
> +=C2=A0 =C2=A0 { "pcm2",=C2=A0 =C2=A0 =C2=A0 0x01c22800, 1 *= KiB },
> +=C2=A0 =C2=A0 { "audio",=C2=A0 =C2=A0 =C2=A00x01c22c00, 2 *= KiB },
> +=C2=A0 =C2=A0 { "smta",=C2=A0 =C2=A0 =C2=A0 0x01c23400, 1 *= KiB },
> +=C2=A0 =C2=A0 { "ths",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c25000= , 1 * KiB },
> +=C2=A0 =C2=A0 { "uart0",=C2=A0 =C2=A0 =C2=A00x01c28000, 1 *= KiB },
> +=C2=A0 =C2=A0 { "uart1",=C2=A0 =C2=A0 =C2=A00x01c28400, 1 *= KiB },
> +=C2=A0 =C2=A0 { "uart2",=C2=A0 =C2=A0 =C2=A00x01c28800, 1 *= KiB },
> +=C2=A0 =C2=A0 { "uart3",=C2=A0 =C2=A0 =C2=A00x01c28c00, 1 *= KiB },
> +=C2=A0 =C2=A0 { "twi0",=C2=A0 =C2=A0 =C2=A0 0x01c2ac00, 1 *= KiB },
> +=C2=A0 =C2=A0 { "twi1",=C2=A0 =C2=A0 =C2=A0 0x01c2b000, 1 *= KiB },
> +=C2=A0 =C2=A0 { "twi2",=C2=A0 =C2=A0 =C2=A0 0x01c2b400, 1 *= KiB },
> +=C2=A0 =C2=A0 { "scr",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c2c400= , 1 * KiB },
> +=C2=A0 =C2=A0 { "emac",=C2=A0 =C2=A0 =C2=A0 0x01c30000, 64 = * KiB },
> +=C2=A0 =C2=A0 { "gpu",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01c40000= , 64 * KiB },
> +=C2=A0 =C2=A0 { "hstmr",=C2=A0 =C2=A0 =C2=A00x01c60000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "dramcom",=C2=A0 =C2=A00x01c62000, 4 * KiB = },
> +=C2=A0 =C2=A0 { "dramctl0",=C2=A0 0x01c63000, 4 * KiB }, > +=C2=A0 =C2=A0 { "dramphy0",=C2=A0 0x01c65000, 4 * KiB }, > +=C2=A0 =C2=A0 { "spi0",=C2=A0 =C2=A0 =C2=A0 0x01c68000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "spi1",=C2=A0 =C2=A0 =C2=A0 0x01c69000, 4 *= KiB },
> +=C2=A0 =C2=A0 { "csi",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01cb0000= , 320 * KiB },
> +=C2=A0 =C2=A0 { "tve",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01e00000= , 64 * KiB },
> +=C2=A0 =C2=A0 { "hdmi",=C2=A0 =C2=A0 =C2=A0 0x01ee0000, 128= * KiB },
> +=C2=A0 =C2=A0 { "rtc",=C2=A0 =C2=A0 =C2=A0 =C2=A00x01f00000= , 1 * KiB },
> +=C2=A0 =C2=A0 { "r_timer",=C2=A0 =C2=A00x01f00800, 1 * KiB = },
> +=C2=A0 =C2=A0 { "r_intc",=C2=A0 =C2=A0 0x01f00c00, 1 * KiB = },
> +=C2=A0 =C2=A0 { "r_wdog",=C2=A0 =C2=A0 0x01f01000, 1 * KiB = },
> +=C2=A0 =C2=A0 { "r_prcm",=C2=A0 =C2=A0 0x01f01400, 1 * KiB = },
> +=C2=A0 =C2=A0 { "r_twd",=C2=A0 =C2=A0 =C2=A00x01f01800, 1 *= KiB },
> +=C2=A0 =C2=A0 { "r_cpucfg",=C2=A0 0x01f01c00, 1 * KiB }, > +=C2=A0 =C2=A0 { "r_cir-rx",=C2=A0 0x01f02000, 1 * KiB }, > +=C2=A0 =C2=A0 { "r_twi",=C2=A0 =C2=A0 =C2=A00x01f02400, 1 *= KiB },
> +=C2=A0 =C2=A0 { "r_uart",=C2=A0 =C2=A0 0x01f02800, 1 * KiB = },
> +=C2=A0 =C2=A0 { "r_pio",=C2=A0 =C2=A0 =C2=A00x01f02c00, 1 *= KiB },
> +=C2=A0 =C2=A0 { "r_pwm",=C2=A0 =C2=A0 =C2=A00x01f03800, 1 *= KiB },
> +=C2=A0 =C2=A0 { "core-dbg",=C2=A0 0x3f500000, 128 * KiB },<= br> > +=C2=A0 =C2=A0 { "tsgen-ro",=C2=A0 0x3f506000, 4 * KiB }, > +=C2=A0 =C2=A0 { "tsgen-ctl", 0x3f507000, 4 * KiB },
> +=C2=A0 =C2=A0 { "ddr-mem",=C2=A0 =C2=A00x40000000, 2 * GiB = },
> +=C2=A0 =C2=A0 { "n-brom",=C2=A0 =C2=A0 0xffff0000, 32 * KiB= },
> +=C2=A0 =C2=A0 { "s-brom",=C2=A0 =C2=A0 0xffff0000, 64 * KiB= }
> +};
> +
> +/* Per Processor Interrupts */
> +enum {
> +=C2=A0 =C2=A0 AW_H3_GIC_PPI_MAINT=C2=A0 =C2=A0 =C2=A0=3D=C2=A0 9,
> +=C2=A0 =C2=A0 AW_H3_GIC_PPI_HYPTIMER=C2=A0 =3D 10,
> +=C2=A0 =C2=A0 AW_H3_GIC_PPI_VIRTTIMER =3D 11,
> +=C2=A0 =C2=A0 AW_H3_GIC_PPI_SECTIMER=C2=A0 =3D 13,
> +=C2=A0 =C2=A0 AW_H3_GIC_PPI_PHYSTIMER =3D 14
> +};
> +
> +/* Shared Processor Interrupts */
> +enum {
> +=C2=A0 =C2=A0 AW_H3_GIC_SPI_UART0=C2=A0 =C2=A0 =C2=A0=3D=C2=A0 0,
> +=C2=A0 =C2=A0 AW_H3_GIC_SPI_UART1=C2=A0 =C2=A0 =C2=A0=3D=C2=A0 1,
> +=C2=A0 =C2=A0 AW_H3_GIC_SPI_UART2=C2=A0 =C2=A0 =C2=A0=3D=C2=A0 2,
> +=C2=A0 =C2=A0 AW_H3_GIC_SPI_UART3=C2=A0 =C2=A0 =C2=A0=3D=C2=A0 3,
> +=C2=A0 =C2=A0 AW_H3_GIC_SPI_TIMER0=C2=A0 =C2=A0 =3D 18,
> +=C2=A0 =C2=A0 AW_H3_GIC_SPI_TIMER1=C2=A0 =C2=A0 =3D 19,
> +};
> +
> +/* Allwinner H3 general constants */
> +enum {
> +=C2=A0 =C2=A0 AW_H3_GIC_NUM_SPI=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 128
> +};
> +
> +static void allwinner_h3_init(Object *obj)
> +{
> +=C2=A0 =C2=A0 AwH3State *s =3D AW_H3(obj);
> +
> +=C2=A0 =C2=A0 s->memmap =3D allwinner_h3_memmap;
> +
> +=C2=A0 =C2=A0 for (int i =3D 0; i < AW_H3_NUM_CPUS; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 object_initialize_child(obj, "cpu[*]= ", &s->cpus[i], sizeof(s->cpus[i]),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ARM_CPU_TYPE_NAME("cortex-a= 7"),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &error_abort, NULL);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "gic", &s->= gic, sizeof(s->gic),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_ARM_GIC);
> +
> +=C2=A0 =C2=A0 sysbus_init_child_obj(obj, "timer", &s-&g= t;timer, sizeof(s->timer),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 TYPE_AW_A10_PIT);
> +=C2=A0 =C2=A0 object_property_add_alias(obj, "clk0-freq", O= BJECT(&s->timer),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "clk0-freq", &error_abort= );
> +=C2=A0 =C2=A0 object_property_add_alias(obj, "clk1-freq", O= BJECT(&s->timer),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "clk1-freq", &error_abort= );
> +}
> +
> +static void allwinner_h3_realize(DeviceState *dev, Error **errp)
> +{
> +=C2=A0 =C2=A0 AwH3State *s =3D AW_H3(dev);
> +=C2=A0 =C2=A0 unsigned i;
> +
> +=C2=A0 =C2=A0 /* CPUs */
> +=C2=A0 =C2=A0 for (i =3D 0; i < AW_H3_NUM_CPUS; i++) {
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Provide Power State Coordination Inter= face */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_prop_set_int32(DEVICE(&s->cpu= s[i]), "psci-conduit",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 QEMU_PSCI_CONDUIT_HVC);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Disable secondary CPUs */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_prop_set_bit(DEVICE(&s->cpus[= i]), "start-powered-off",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 i > 0);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* All exception levels required */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_prop_set_bit(DEVICE(&s->cpus[= i]), "has_el3", true);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_prop_set_bit(DEVICE(&s->cpus[= i]), "has_el2", true);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Mark realized */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_init_nofail(DEVICE(&s->cpus[i= ]));
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Generic Interrupt Controller */
> +=C2=A0 =C2=A0 qdev_prop_set_uint32(DEVICE(&s->gic), "num-= irq", AW_H3_GIC_NUM_SPI +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0GIC_INTERNAL);
> +=C2=A0 =C2=A0 qdev_prop_set_uint32(DEVICE(&s->gic), "revi= sion", 2);
> +=C2=A0 =C2=A0 qdev_prop_set_uint32(DEVICE(&s->gic), "num-= cpu", AW_H3_NUM_CPUS);
> +=C2=A0 =C2=A0 qdev_prop_set_bit(DEVICE(&s->gic), "has-sec= urity-extensions", false);
> +=C2=A0 =C2=A0 qdev_prop_set_bit(DEVICE(&s->gic), "has-vir= tualization-extensions", true);
> +=C2=A0 =C2=A0 qdev_init_nofail(DEVICE(&s->gic));
> +
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s-&g= t;memmap[AW_H3_GIC_DIST]);
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s-&g= t;memmap[AW_H3_GIC_CPU]);
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s-&g= t;memmap[AW_H3_GIC_HYP]);
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s-&g= t;memmap[AW_H3_GIC_VCPU]);
> +
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* Wire the outputs from each CPU's generic ti= mer and the GICv3
> +=C2=A0 =C2=A0 =C2=A0* maintenance interrupt signal to the appropriate= GIC PPI inputs,
> +=C2=A0 =C2=A0 =C2=A0* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt o= utputs to the CPU's inputs.
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 for (i =3D 0; i < AW_H3_NUM_CPUS; i++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 DeviceState *cpudev =3D DEVICE(&s->= ;cpus[i]);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int ppibase =3D AW_H3_GIC_NUM_SPI + i * G= IC_INTERNAL + GIC_NR_SGIS;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 int irq;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Mapping from the output timer irq= lines from the CPU to the
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* GIC PPI inputs used for this boar= d.
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 const int timer_irq[] =3D {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_PHYS] =3D AW_H3_GIC= _PPI_PHYSTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_VIRT] =3D AW_H3_GIC= _PPI_VIRTTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_HYP]=C2=A0 =3D AW_H= 3_GIC_PPI_HYPTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 [GTIMER_SEC]=C2=A0 =3D AW_H= 3_GIC_PPI_SECTIMER,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 };
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Connect CPU timer outputs to GIC PPI i= nputs */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (irq =3D 0; irq < ARRAY_SIZE(timer= _irq); irq++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_connect_gpio_out(cpude= v, irq,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_get_gpio_in(DEVICE(&= amp;s->gic),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ppibase + timer_irq[irq]));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Connect GIC outputs to CPU interrupt i= nputs */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s-= >gic), i,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s-= >gic), i + AW_H3_NUM_CPUS,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s-= >gic), i + (2 * AW_H3_NUM_CPUS),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s-= >gic), i + (3 * AW_H3_NUM_CPUS),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* GIC maintenance signal */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s-= >gic), i + (4 * AW_H3_NUM_CPUS),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_get_gpio_in(DEVICE(&s->gic),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 ppibase + AW_H3_GIC_PPI_MAINT));
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Timer */
> +=C2=A0 =C2=A0 qdev_init_nofail(DEVICE(&s->timer));
> +=C2=A0 =C2=A0 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s-= >memmap[AW_H3_PIT]);
> +=C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0= ));
> +=C2=A0 =C2=A0 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1= ));
> +
> +=C2=A0 =C2=A0 /* SRAM */
> +=C2=A0 =C2=A0 memory_region_init_ram(&s->sram_a1, OBJECT(dev),= "sram A1",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 64 * KiB, &error_abort);
> +=C2=A0 =C2=A0 memory_region_init_ram(&s->sram_a2, OBJECT(dev),= "sram A2",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 32 * KiB, &error_abort);
> +=C2=A0 =C2=A0 memory_region_init_ram(&s->sram_c, OBJECT(dev), = "sram C",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 44 * KiB, &error_abort);
> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), s->= memmap[AW_H3_SRAM_A1],
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sram_a1);
> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), s->= memmap[AW_H3_SRAM_A2],
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sram_a2);
> +=C2=A0 =C2=A0 memory_region_add_subregion(get_system_memory(), s->= memmap[AW_H3_SRAM_C],
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &s->sram_c);
> +
> +=C2=A0 =C2=A0 /* UART0. For future clocktree API: All UARTS are conne= cted to APB2_CLK. */
> +=C2=A0 =C2=A0 serial_mm_init(get_system_memory(), s->memmap[AW_H3_= UART0], 2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
> +=C2=A0 =C2=A0 /* UART1 */
> +=C2=A0 =C2=A0 serial_mm_init(get_system_memory(), s->memmap[AW_H3_= UART1], 2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
> +=C2=A0 =C2=A0 /* UART2 */
> +=C2=A0 =C2=A0 serial_mm_init(get_system_memory(), s->memmap[AW_H3_= UART2], 2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
> +=C2=A0 =C2=A0 /* UART3 */
> +=C2=A0 =C2=A0 serial_mm_init(get_system_memory(), s->memmap[AW_H3_= UART3], 2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
> +
> +=C2=A0 =C2=A0 /* Unimplemented devices */
> +=C2=A0 =C2=A0 for (i =3D 0; i < ARRAY_SIZE(unimplemented); i++) {<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 create_unimplemented_device(unimplemented= [i].device_name,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unimplemented[i].b= ase,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unimplemented[i].s= ize);
> +=C2=A0 =C2=A0 }
> +}
> +
> +static void allwinner_h3_class_init(ObjectClass *oc, void *data)
> +{
> +=C2=A0 =C2=A0 DeviceClass *dc =3D DEVICE_CLASS(oc);
> +
> +=C2=A0 =C2=A0 dc->realize =3D allwinner_h3_realize;
> +=C2=A0 =C2=A0 /* Reason: uses serial_hds and nd_table */

Maybe use "serial_hd()". Also nd_table is not used yet.

Thanks, this comment was outdated indeed, I'= ll correct it.
=C2=A0

> +=C2=A0 =C2=A0 dc->user_creatable =3D false;
> +}
> +
> +static const TypeInfo allwinner_h3_type_info =3D {
> +=C2=A0 =C2=A0 .name =3D TYPE_AW_H3,
> +=C2=A0 =C2=A0 .parent =3D TYPE_DEVICE,
> +=C2=A0 =C2=A0 .instance_size =3D sizeof(AwH3State),
> +=C2=A0 =C2=A0 .instance_init =3D allwinner_h3_init,
> +=C2=A0 =C2=A0 .class_init =3D allwinner_h3_class_init,
> +};
> +
> +static void allwinner_h3_register_types(void)
> +{
> +=C2=A0 =C2=A0 type_register_static(&allwinner_h3_type_info);
> +}
> +
> +type_init(allwinner_h3_register_types)
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 55d3642e6c..225582704d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -481,6 +481,13 @@ F: hw/*/allwinner*
>=C2=A0 =C2=A0F: include/hw/*/allwinner*
>=C2=A0 =C2=A0F: hw/arm/cubieboard.c
>=C2=A0 =C2=A0
> +Allwinner-h3
> +M: Niek Linnenbank <nieklinnenbank@gmail.com>
> +L: qemu-arm@= nongnu.org
> +S: Maintained
> +F: hw/*/allwinner-h3*
> +F: include/hw/*/allwinner-h3*
> +
>=C2=A0 =C2=A0ARM PrimeCell and CMSDK devices
>=C2=A0 =C2=A0M: Peter Maydell <peter.maydell@linaro.org>
>=C2=A0 =C2=A0L: qemu-arm@nongnu.org
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 3d86691ae0..bb75c1de17 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -295,6 +295,14 @@ config ALLWINNER_A10
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select SERIAL
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select UNIMP
>=C2=A0 =C2=A0
> +config ALLWINNER_H3
> +=C2=A0 =C2=A0 bool
> +=C2=A0 =C2=A0 select ALLWINNER_A10_PIT

We should now rename this as ALLWINNER_PIT.

=
I see your point, now both SoCs are using the A10 specific PIT timer.<= /div>
Previously we agreed to do the generalization of that timer in a = separate patch series.
I think it makes sense to also do the rena= me of this item as part of that separate series.
=C2=A0
=

> +=C2=A0 =C2=A0 select SERIAL
> +=C2=A0 =C2=A0 select ARM_TIMER
> +=C2=A0 =C2=A0 select ARM_GIC
> +=C2=A0 =C2=A0 select UNIMP
> +
>=C2=A0 =C2=A0config RASPI
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool
>=C2=A0 =C2=A0 =C2=A0 =C2=A0select FRAMEBUFFER
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 336f6dd374..ae577e875f 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -35,6 +35,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o
>=C2=A0 =C2=A0obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o
>=C2=A0 =C2=A0obj-$(CONFIG_STRONGARM) +=3D strongarm.o
>=C2=A0 =C2=A0obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboar= d.o
> +obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o
>=C2=A0 =C2=A0obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o r= aspi.o
>=C2=A0 =C2=A0obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o
>=C2=A0 =C2=A0obj-$(CONFIG_STM32F405_SOC) +=3D stm32f405_soc.o
>

Patch very clean!

Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>

Thanks for reviewing Philippe!

Regards,
Niek
=C2=A0


--
Niek Linnenbank

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