Re: [PATCH] target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction

[Vasilis Liaskovitis <vliaskovitis@suse.com>]

Hi,

On Wed, Jun 18, 2025 at 4:22 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
> > +    if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0) ||
> > +        (cpu->cfg.rvv_vsetvl_x0_vill && x0 && (env->vl != vl))) {
>
> In this particular case I don't mind replicating code. The first existing check can be
> left untouched, exiting early before spending time calculating vlmax and vl.
>
> We can then add the new check that depends on vl here, even if we end up copying those
> few "env->something =" lines again. If you really want to avoid code duplication I
> wouldn't oppose adding a 'vill' label and using 'goto' as an alternative of duplicating
> those 6 lines.

thank you for the review. I sent a v2 simply duplicating the code.

thanks,

- Vasilis

>
>
> Patch LGTM otherwise. Thanks,
>
>
> Daniel
>
> > +        /* only set vill bit. */
> > +        env->vill = 1;
> > +        env->vtype = 0;
> > +        env->vl = 0;
> > +        env->vstart = 0;
> > +        return 0;
> > +    }
> > +
> >       env->vl = vl;
> >       env->vtype = s2;
> >       env->vstart = 0;
>