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From: Peter Crosthwaite <crosthwaitepeter@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar Iglesias" <edgar.iglesias@xilinx.com>,
	"Edgar Iglesias" <edgar.iglesias@gmail.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Andreas Färber" <afaerber@suse.de>,
	"Alistair Francis" <alistair.francis@xilinx.com>
Subject: Re: [Qemu-devel] [PATCH v1 00/15] data-driven device registers
Date: Tue, 15 Dec 2015 12:52:41 -0800	[thread overview]
Message-ID: <CAPokK=p4BLhsPi1vb_OxAmPQz4r1EL9G1V3kgqx5t-ZKRsfOZw@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA_3c2HVz9ih9Zya8qT62YnFe1=+iK9_5BEn8Y9pb2udwQ@mail.gmail.com>

On Tue, Dec 15, 2015 at 11:46 AM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> On 30 October 2015 at 08:06, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 30 October 2015 at 06:52, Peter Crosthwaite
>> <crosthwaitepeter@gmail.com> wrote:
>>> Ping^3
>>>
>>> This has been on list for a very long time without 3rd party review.
>>> Can I send a PULL?
>>
>> I would prefer not to take a new unreviewed feature
>> in softfreeze for 2.5...
>
> Since we're now about to come out of 2.5 freeze I guess I
> should write something about this patchset. I don't have any
> fundamental objections to it, but it doesn't really excite me
> either. I would like to see it reviewed by somebody else who
> does think it's a good idea, because I think that increases
> the chances that we will get general use of the facilities
> rather than it being an odd thing used by a few Xilinx device
> models and nothing else.
>

It needs to exist before it can be used so there is a bit of a chicken
and egg problem there. It is originally my code and Alistair has taken
ownership of it so that excludes the both of us. Aside from yourself,
there aren't too many new device-model authors out there who are
active review. Do you have a nominee?

It is a developer-centric feature as you can do things like gen device
model templates from data. The philosophy here (which is contrary to
most maintainers thinking) is that hardware designers and people who
constantly change hardware design specs and create new bits of IP are
the consumer of QEMU and the QEMU source code is a consumable. So I
see why it is hard to excite your regular QEMU developer who is
thinking purely about non-engineering end consumers.

I'll throw a new argument into the mix that is closer to home for
yourself, it has a lot in common with the ARM CP API. If we converted
the ARM CP API to be data driven rather than code driven (which we
have), why are MMIO devices so different? CP accesses can be
side-effectless or require side-effect causing functions, and 99% of
sysbus devices fit this description. Ideally, I'd like to mass-covert
CP API to use something like this for one API to rule them all. If I
instead morphed the CP API to a generic feature in hw/core, extended
with the features of this patch set, would that work better for you?
Then both devices and custom register APIs (like CP) can be
standardised. Note that this is already two layered. The concept of
the register API which defines collections of registers is separate
from sysbus.

Regards,
Peter

> I hope that makes sense and doesn't seem too arbitrary a
> hurdle to make you jump?
>
> thanks
> -- PMM

  reply	other threads:[~2015-12-15 20:52 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-29 20:24 [Qemu-devel] [PATCH v1 00/15] data-driven device registers Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 01/15] register: Add Register API Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 02/15] register: Add Memory API glue Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 03/15] register: Add support for decoding information Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 04/15] register: Define REG and FIELD macros Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 05/15] register: QOMify Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 06/15] register: Add block initialise helper Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 07/15] bitops: Add ONES macro Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 08/15] dma: Add Xilinx Zynq devcfg device model Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 09/15] xilinx_zynq: add devcfg to machine model Alistair Francis
2015-07-29 20:24 ` [Qemu-devel] [PATCH v1 10/15] qdev: Define qdev_get_gpio_out Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 11/15] qdev: Add qdev_pass_all_gpios API Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 12/15] irq: Add opaque setter routine Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 13/15] register: Add GPIO API Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 14/15] misc: Introduce ZynqMP IOU SLCR Alistair Francis
2015-07-29 20:25 ` [Qemu-devel] [PATCH v1 15/15] xlnx-zynqmp: Connect the " Alistair Francis
2015-08-27 21:47 ` [Qemu-devel] [PATCH v1 00/15] data-driven device registers Alistair Francis
2015-10-14 18:42   ` Alistair Francis
2015-10-30  6:52     ` Peter Crosthwaite
2015-10-30  8:06       ` Peter Maydell
2015-12-15 19:46         ` Peter Maydell
2015-12-15 20:52           ` Peter Crosthwaite [this message]
2015-12-15 21:56             ` Peter Maydell
2015-12-16 16:33               ` Alistair Francis
2016-01-08  0:39                 ` Alistair Francis
2016-01-08 10:40                   ` Peter Maydell
2016-01-08 11:05                     ` Edgar E. Iglesias
2016-01-19 19:51                       ` Alistair Francis
2016-01-19 21:35                         ` Edgar E. Iglesias
2016-01-28 16:31                     ` Frederic Konrad
2016-01-28 16:34                       ` Peter Maydell
2016-01-30  0:56                         ` Alistair Francis

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