[PATCH for-11.0 v3 0/8] hw/arm/smmuv3-accel: Support AUTO properties

[PATCH for-11.0 v3 0/8] hw/arm/smmuv3-accel: Support AUTO properties

[Nathan Chen]

Hi,

This is a follow-up to the previous series [0] that introduces support
for specifying 'auto' for arm-smmuv3 accelerated mode's ATS, RIL,
SSIDSIZE, and OAS feature properties.

In QEMU 11.0 we introduced new options for vSMMU [1], but feedback received
when starting the integration of layered products shows the need for
auto/host-retrieved values. To avoid breaking JSON/QMP compat, we want
to fix the option types so that they can later support the auto mode. At
the moment the auto mode is not supported though.

A future series will introduce support for resolving the 'auto' values
based on host SMMUv3 IDR values, as well as setting per-device ATS
capability.

A complete branch can be found here:
https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-v3

Please take a look and let me know your feedback.

Thanks,
Nathan

Changes from v2:
- Enforce 'auto' value not being supported for HW-accel SMMUv3 props
- Revise docs to mention auto is not supported and these properties
  are only applicable when accel=on.
- Only override non-defaults in smmuv3_accel_idr_override()
- Remove check for SSIDSIZE AUTO in smmuv3_accel_idr_override() as
  smmu_validate_property() checks for AUTO beforehand
- Consolidate comments for ssidsize_mode_to_value()
- Include Fixes tags in commit descriptions
- Include R-by tags from v2

Changes from RFCv1:
- Remove changes that resolve the 'auto' values based on host SMMUv3
- Restore defaults values for RIL, OAS, SSIDSIZE, and ATS
- Update OasMode to accept all OAS sizes instead of only auto, 44, and
  48
- Include comment in SsidSizeMode schema clarifying enum value
  ordering
- Replace ats-enabled prop with a helper that accepts the dynamic
  casted TYPE_ARM_SMMUV3 object
- Separate out guest vs. host ATS check in
  smmuv3_accel_check_hw_compatible() to a different commit
- Document accel, RIL, OAS, SSIDSIZE, and ATS properties in
  qemu-options.hx

Testing:
Basic sanity testing was performed on an NVIDIA Grace platform with GPU
device assignment and running CUDA test apps on the guest. Additional
testing and feedback are welcome.

[0] https://lore.kernel.org/qemu-devel/20260312210328.2016191-1-nathanc@nvidia.com/
[1] https://lore.kernel.org/all/20260126104342.253965-1-skolothumtho@nvidia.com/

Nathan Chen (8):
  hw/arm/smmuv3-accel: Check ATS compatibility between host and guest
  hw/arm/smmuv3-accel: Change ATS property to OnOffAuto
  hw/arm/smmuv3-accel: Change RIL property to OnOffAuto
  qdev: Add a SsidSizeMode property
  hw/arm/smmuv3-accel: Change SSIDSIZE property to SsidSizeMode
  qdev: Add an OasMode property
  hw/arm/smmuv3-accel: Change OAS property to OasMode
  qemu-options.hx: Document arm-smmuv3 device's accel properties

 hw/arm/smmuv3-accel.c                    | 43 ++++++++++++++++++----
 hw/arm/smmuv3.c                          | 45 ++++++++++++++++--------
 hw/arm/virt-acpi-build.c                 |  2 +-
 hw/core/qdev-properties-system.c         | 27 ++++++++++++++
 include/hw/arm/smmuv3.h                  | 11 +++---
 include/hw/core/qdev-properties-system.h |  6 ++++
 qapi/misc-arm.json                       | 44 +++++++++++++++++++++++
 qapi/pragma.json                         |  1 +
 qemu-options.hx                          | 35 +++++++++++++++++-
 9 files changed, 187 insertions(+), 27 deletions(-)

-- 
2.43.0

[PATCH v3 1/8] hw/arm/smmuv3-accel: Check ATS compatibility between host and guest

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Compare the host SMMUv3 ATS support bit with the guest SMMUv3 ATS support
bit in IDR0 and fail the compatibility check if ATS support is opted as
enabled on the guest SMMUv3 when it is not supported on host SMMUv3.

Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS")
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 17306cd04b..2bb142c47f 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -101,6 +101,12 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s,
                    smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS)));
         return false;
     }
+    /* Check ATS value opted is compatible with Host SMMUv3 */
+    if (FIELD_EX32(info->idr[0], IDR0, ATS) <
+                FIELD_EX32(s->idr[0], IDR0, ATS)) {
+        error_setg(errp, "Host SMMUv3 doesn't support Address Translation Services");
+        return false;
+    }
 
     /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */
     if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) !=
-- 
2.43.0

[PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to OnOffAuto

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto'
value is not implemented, as this commit is meant to set the property
to the correct type and avoid breaking JSON/QMP when the auto mode is
introduced. A future patch will implement resolution of the 'auto'
value to match the host SMMUv3 ATS support.

Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS")
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c    |  6 ++++--
 hw/arm/smmuv3.c          | 14 ++++++++++++--
 hw/arm/virt-acpi-build.c |  2 +-
 include/hw/arm/smmuv3.h  |  4 +++-
 4 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 2bb142c47f..621ac531a5 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -826,8 +826,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
     /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */
     s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril);
 
-    /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */
-    s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, s->ats);
+    /* Only override ATS if user explicitly set ON */
+    if (s->ats == ON_OFF_AUTO_ON) {
+        s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1);
+    }
 
     /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */
     if (s->oas == SMMU_OAS_48BIT) {
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 068108e49b..3dead0bcd3 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s)
     smmuv3_accel_idr_override(s);
 }
 
+bool smmuv3_ats_enabled(SMMUv3State *s)
+{
+    return FIELD_EX32(s->idr[0], IDR0, ATS);
+}
+
 static void smmuv3_reset(SMMUv3State *s)
 {
     s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
@@ -1971,7 +1976,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
             error_setg(errp, "ril can only be disabled if accel=on");
             return false;
         }
-        if (s->ats) {
+        if (s->ats == ON_OFF_AUTO_ON) {
             error_setg(errp, "ats can only be enabled if accel=on");
             return false;
         }
@@ -1993,6 +1998,11 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
         return false;
     }
 
+    if (s->ats == ON_OFF_AUTO_AUTO) {
+        error_setg(errp, "ats cannot be set to auto");
+        return false;
+    }
+
     if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
         error_setg(errp, "OAS can only be set to 44 or 48 bits");
         return false;
@@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] = {
     DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0),
     /* RIL can be turned off for accel cases */
     DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true),
-    DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false),
+    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF),
     DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
     DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0),
 };
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 719d2f994e..591cfc993c 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaque)
 
     bus = PCI_BUS(object_property_get_link(obj, "primary-bus", &error_abort));
     sdev.accel = object_property_get_bool(obj, "accel", &error_abort);
-    sdev.ats = object_property_get_bool(obj, "ats", &error_abort);
+    sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));
     pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
     sbdev = SYS_BUS_DEVICE(obj);
     sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index 26b2fc42fd..ce51a5b9b4 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -70,7 +70,7 @@ struct SMMUv3State {
     uint64_t msi_gpa;
     Error *migration_blocker;
     bool ril;
-    bool ats;
+    OnOffAuto ats;
     uint8_t oas;
     uint8_t ssidsize;
 };
@@ -91,6 +91,8 @@ struct SMMUv3Class {
     ResettablePhases parent_phases;
 };
 
+bool smmuv3_ats_enabled(struct SMMUv3State *s);
+
 #define TYPE_ARM_SMMUV3   "arm-smmuv3"
 OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
 
-- 
2.43.0

[PATCH v3 3/8] hw/arm/smmuv3-accel: Change RIL property to OnOffAuto

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Change accel SMMUv3 RIL property from bool to OnOffAuto. The 'auto'
value is not implemented, as this commit is meant to set the property
to the correct type and avoid breaking JSON/QMP when the auto mode is
introduced. A future patch will implement resolution of the 'auto'
value to match the host SMMUv3 RIL support.

Fixes: bd715ff5bda9 ("hw/arm/smmuv3-accel: Add a property to specify RIL support")
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c   | 6 ++++--
 hw/arm/smmuv3.c         | 9 +++++++--
 include/hw/arm/smmuv3.h | 2 +-
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 621ac531a5..ddd927fa80 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -823,8 +823,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
         return;
     }
 
-    /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */
-    s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril);
+    /* Only override RIL if user explicitly set OFF */
+    if (s->ril == ON_OFF_AUTO_OFF) {
+        s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 0);
+    }
 
     /* Only override ATS if user explicitly set ON */
     if (s->ats == ON_OFF_AUTO_ON) {
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 3dead0bcd3..40d6aca83e 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1972,7 +1972,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
 #endif
 
     if (!s->accel) {
-        if (!s->ril) {
+        if (s->ril == ON_OFF_AUTO_OFF) {
             error_setg(errp, "ril can only be disabled if accel=on");
             return false;
         }
@@ -2003,6 +2003,11 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
         return false;
     }
 
+    if (s->ril == ON_OFF_AUTO_AUTO) {
+        error_setg(errp, "ril cannot be set to auto");
+        return false;
+    }
+
     if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
         error_setg(errp, "OAS can only be set to 44 or 48 bits");
         return false;
@@ -2137,7 +2142,7 @@ static const Property smmuv3_properties[] = {
     /* GPA of MSI doorbell, for SMMUv3 accel use. */
     DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0),
     /* RIL can be turned off for accel cases */
-    DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true),
+    DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON),
     DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF),
     DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
     DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0),
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index ce51a5b9b4..c35e599bbc 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -69,7 +69,7 @@ struct SMMUv3State {
     struct SMMUv3AccelState *s_accel;
     uint64_t msi_gpa;
     Error *migration_blocker;
-    bool ril;
+    OnOffAuto ril;
     OnOffAuto ats;
     uint8_t oas;
     uint8_t ssidsize;
-- 
2.43.0

[PATCH v3 4/8] qdev: Add a SsidSizeMode property

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Introduce a new enum type property allowing to set a Substream ID size
for HW-accelerated smmuv3. Values are auto and 0..20. The auto value
allows SSID size property to be derived from host IOMMU capabilities.
A value of 0 disables SubstreamID, while non-zero values specify the
SSID size in bits.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/core/qdev-properties-system.c         | 14 ++++++++++++++
 include/hw/core/qdev-properties-system.h |  3 +++
 qapi/misc-arm.json                       | 16 ++++++++++++++++
 qapi/pragma.json                         |  1 +
 4 files changed, 34 insertions(+)

diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index a402321f42..4aca1d4326 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -18,6 +18,7 @@
 #include "qapi/qapi-types-block.h"
 #include "qapi/qapi-types-machine.h"
 #include "qapi/qapi-types-migration.h"
+#include "qapi/qapi-types-misc-arm.h"
 #include "qapi/qapi-visit-virtio.h"
 #include "qapi/qmp/qerror.h"
 #include "qemu/ctype.h"
@@ -723,6 +724,19 @@ const PropertyInfo qdev_prop_zero_page_detection = {
     .set_default_value = qdev_propinfo_set_default_value_enum,
 };
 
+/* --- SsidSizeMode --- */
+
+QEMU_BUILD_BUG_ON(sizeof(SsidSizeMode) != sizeof(int));
+
+const PropertyInfo qdev_prop_ssidsize_mode = {
+    .type = "SsidSizeMode",
+    .description = "ssidsize mode: auto, 0-20",
+    .enum_table = &SsidSizeMode_lookup,
+    .get = qdev_propinfo_get_enum,
+    .set = qdev_propinfo_set_enum,
+    .set_default_value = qdev_propinfo_set_default_value_enum,
+};
+
 /* --- Reserved Region --- */
 
 /*
diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qdev-properties-system.h
index ec21732ce5..4708885164 100644
--- a/include/hw/core/qdev-properties-system.h
+++ b/include/hw/core/qdev-properties-system.h
@@ -14,6 +14,7 @@ extern const PropertyInfo qdev_prop_multifd_compression;
 extern const PropertyInfo qdev_prop_mig_mode;
 extern const PropertyInfo qdev_prop_granule_mode;
 extern const PropertyInfo qdev_prop_zero_page_detection;
+extern const PropertyInfo qdev_prop_ssidsize_mode;
 extern const PropertyInfo qdev_prop_losttickpolicy;
 extern const PropertyInfo qdev_prop_blockdev_on_error;
 extern const PropertyInfo qdev_prop_bios_chs_trans;
@@ -61,6 +62,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_list;
 #define DEFINE_PROP_ZERO_PAGE_DETECTION(_n, _s, _f, _d) \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_zero_page_detection, \
                        ZeroPageDetection)
+#define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \
+    DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMode)
 #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \
                         LostTickPolicy)
diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json
index f921d740f1..76ea0a09fa 100644
--- a/qapi/misc-arm.json
+++ b/qapi/misc-arm.json
@@ -45,3 +45,19 @@
 #                     { "version": 3, "emulated": false, "kernel": true } ] }
 ##
 { 'command': 'query-gic-capabilities', 'returns': ['GICCapability'] }
+
+##
+# @SsidSizeMode:
+#
+# SMMUv3 SubstreamID size configuration mode.
+#
+# @auto: derive from host IOMMU capabilities
+#
+# Values 0-20: SSIDSIZE value in bits.  0 disables SubstreamID.
+#
+# Since: 11.0
+##
+{ 'enum': 'SsidSizeMode',
+  'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+            '10', '11', '12', '13', '14', '15', '16', '17', '18',
+            '19', '20' ] } # order matters, see ssid_size_mode_auto()
diff --git a/qapi/pragma.json b/qapi/pragma.json
index 193bc39059..24aebbe8f5 100644
--- a/qapi/pragma.json
+++ b/qapi/pragma.json
@@ -68,6 +68,7 @@
         'S390CpuEntitlement',
         'S390CpuPolarization',
         'S390CpuState',
+        'SsidSizeMode',
         'String',
         'StringWrapper',
         'SysEmuTarget',
-- 
2.43.0

[PATCH v3 5/8] hw/arm/smmuv3-accel: Change SSIDSIZE property to SsidSizeMode

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Change accel SMMUv3 SSIDSIZE property from uint8_t to SsidSizeMode.
The 'auto' value is not implemented, as this commit is meant to set the
property to the correct type and avoid breaking JSON/QMP when the auto
mode is introduced. A future patch will implement resolution of 'auto'
value to match the host SMMUv3 SSIDSIZE value.

Fixes: b8c6f8a69d27 ("hw/arm/smmuv3-accel: Make SubstreamID support configurable")
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c   | 23 +++++++++++++++++++++--
 hw/arm/smmuv3.c         | 18 ++++++++++--------
 include/hw/arm/smmuv3.h |  3 ++-
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index ddd927fa80..c90fa9f5bb 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -802,7 +802,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)
     SMMUState *bs = opaque;
     SMMUv3State *s = ARM_SMMUV3(bs);
 
-    if (s->ssidsize) {
+    if (s->ssidsize > SSID_SIZE_MODE_0) {
         flags |= VIOMMU_FLAG_PASID_SUPPORTED;
     }
     return flags;
@@ -817,6 +817,22 @@ static const PCIIOMMUOps smmuv3_accel_ops = {
     .get_msi_direct_gpa = smmuv3_accel_get_msi_gpa,
 };
 
+/*
+ * This returns the value of a SsidSizeMode value offset by 1 to
+ * account for the enum values offset by 1 from actual values.
+ *
+ * SSID_SIZE_MODE_0 = 1, SSID_SIZE_MODE_1 = 2, etc. so return 0
+ * if SSID_SIZE_MODE_0 is passed as input, return 1 if
+ * SSID_SIZE_MODE_1 is passed as input, etc.
+ */
+static uint8_t ssidsize_mode_to_value(SsidSizeMode mode)
+{
+    if (mode == SSID_SIZE_MODE_AUTO) {
+        return 0;
+    }
+    return mode - 1;
+}
+
 void smmuv3_accel_idr_override(SMMUv3State *s)
 {
     if (!s->accel) {
@@ -842,7 +858,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
      * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if user
      * has enabled it.
      */
-    s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize);
+    if (s->ssidsize > SSID_SIZE_MODE_0) {
+        s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,
+                               ssidsize_mode_to_value(s->ssidsize));
+    }
 }
 
 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 40d6aca83e..e7fec7a69e 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -20,6 +20,7 @@
 #include "qemu/bitops.h"
 #include "hw/core/irq.h"
 #include "hw/core/sysbus.h"
+#include "hw/core/qdev-properties-system.h"
 #include "migration/blocker.h"
 #include "migration/vmstate.h"
 #include "hw/core/qdev-properties.h"
@@ -625,7 +626,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
     }
 
     /* Multiple context descriptors require SubstreamID support */
-    if (!s->ssidsize && STE_S1CDMAX(ste) != 0) {
+    if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {
         qemu_log_mask(LOG_UNIMP,
                 "SMMUv3: multiple S1 context descriptors require SubstreamID support. "
                 "Configure ssidsize > 0 (requires accel=on)\n");
@@ -1984,7 +1985,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
             error_setg(errp, "OAS must be 44 bits when accel=off");
             return false;
         }
-        if (s->ssidsize) {
+        if (s->ssidsize > SSID_SIZE_MODE_0) {
             error_setg(errp, "ssidsize can only be set if accel=on");
             return false;
         }
@@ -2008,13 +2009,13 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
         return false;
     }
 
-    if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
-        error_setg(errp, "OAS can only be set to 44 or 48 bits");
+    if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
+        error_setg(errp, "ssidsize cannot be set to auto");
         return false;
     }
-    if (s->ssidsize > SMMU_SSID_MAX_BITS) {
-        error_setg(errp, "ssidsize must be in the range 0 to %d",
-                   SMMU_SSID_MAX_BITS);
+
+    if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
+        error_setg(errp, "OAS can only be set to 44 or 48 bits");
         return false;
     }
 
@@ -2145,7 +2146,8 @@ static const Property smmuv3_properties[] = {
     DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON),
     DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF),
     DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
-    DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0),
+    DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize,
+                              SSID_SIZE_MODE_0),
 };
 
 static void smmuv3_instance_init(Object *obj)
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index c35e599bbc..ddf472493d 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -21,6 +21,7 @@
 
 #include "hw/arm/smmu-common.h"
 #include "qom/object.h"
+#include "qapi/qapi-types-misc-arm.h"
 
 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
 
@@ -72,7 +73,7 @@ struct SMMUv3State {
     OnOffAuto ril;
     OnOffAuto ats;
     uint8_t oas;
-    uint8_t ssidsize;
+    SsidSizeMode ssidsize;
 };
 
 typedef enum {
-- 
2.43.0

[PATCH v3 6/8] qdev: Add an OasMode property

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Introduce a new enum type property allowing to set an Output Address
Size. Values are auto, 32, 36, 40, 42, 44, 48, 52, and 56, where a
value of N specifies an N-bit OAS.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/core/qdev-properties-system.c         | 13 +++++++++++
 include/hw/core/qdev-properties-system.h |  3 +++
 qapi/misc-arm.json                       | 28 ++++++++++++++++++++++++
 3 files changed, 44 insertions(+)

diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c
index 4aca1d4326..a805ee2e1f 100644
--- a/hw/core/qdev-properties-system.c
+++ b/hw/core/qdev-properties-system.c
@@ -737,6 +737,19 @@ const PropertyInfo qdev_prop_ssidsize_mode = {
     .set_default_value = qdev_propinfo_set_default_value_enum,
 };
 
+/* --- OasMode --- */
+
+QEMU_BUILD_BUG_ON(sizeof(OasMode) != sizeof(int));
+
+const PropertyInfo qdev_prop_oas_mode = {
+    .type = "OasMode",
+    .description = "oas mode: auto, 32, 36, 40, 42, 44, 48, 52, 56",
+    .enum_table = &OasMode_lookup,
+    .get = qdev_propinfo_get_enum,
+    .set = qdev_propinfo_set_enum,
+    .set_default_value = qdev_propinfo_set_default_value_enum,
+};
+
 /* --- Reserved Region --- */
 
 /*
diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qdev-properties-system.h
index 4708885164..2cbea16d61 100644
--- a/include/hw/core/qdev-properties-system.h
+++ b/include/hw/core/qdev-properties-system.h
@@ -15,6 +15,7 @@ extern const PropertyInfo qdev_prop_mig_mode;
 extern const PropertyInfo qdev_prop_granule_mode;
 extern const PropertyInfo qdev_prop_zero_page_detection;
 extern const PropertyInfo qdev_prop_ssidsize_mode;
+extern const PropertyInfo qdev_prop_oas_mode;
 extern const PropertyInfo qdev_prop_losttickpolicy;
 extern const PropertyInfo qdev_prop_blockdev_on_error;
 extern const PropertyInfo qdev_prop_bios_chs_trans;
@@ -64,6 +65,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_list;
                        ZeroPageDetection)
 #define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMode)
+#define DEFINE_PROP_OAS_MODE(_n, _s, _f, _d) \
+    DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_oas_mode, OasMode)
 #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \
     DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \
                         LostTickPolicy)
diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json
index 76ea0a09fa..5dbb4add91 100644
--- a/qapi/misc-arm.json
+++ b/qapi/misc-arm.json
@@ -61,3 +61,31 @@
   'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
             '10', '11', '12', '13', '14', '15', '16', '17', '18',
             '19', '20' ] } # order matters, see ssid_size_mode_auto()
+
+##
+# @OasMode:
+#
+# SMMUv3 Output Address Size configuration mode.
+#
+# @auto: derive from host IOMMU capabilities
+#
+# @32: 32-bit output address size
+#
+# @36: 36-bit output address size
+#
+# @40: 40-bit output address size
+#
+# @42: 42-bit output address size
+#
+# @44: 44-bit output address size
+#
+# @48: 48-bit output address size
+#
+# @52: 52-bit output address size
+#
+# @56: 56-bit output address size
+#
+# Since: 11.0
+##
+{ 'enum': 'OasMode',
+  'data': [ 'auto', '32', '36', '40', '42', '44', '48', '52', '56' ] }
-- 
2.43.0

[PATCH v3 7/8] hw/arm/smmuv3-accel: Change OAS property to OasMode

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Change accel SMMUv3 OAS property from uint8_t to OasMode. The
'auto' value is not implemented, as this commit is meant to
set the property to the correct type and avoid breaking JSON/QMP
when the auto mode is introduced. A future patch will implement
resolution of 'auto' value to match the host SMMUv3 OAS value.

Fixes: a015ac990fd3 ("hw/arm/smmuv3-accel: Add property to specify OAS bits")
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c   | 2 +-
 hw/arm/smmuv3.c         | 6 +++---
 include/hw/arm/smmuv3.h | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index c90fa9f5bb..08a4e2a1c8 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -850,7 +850,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
     }
 
     /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */
-    if (s->oas == SMMU_OAS_48BIT) {
+    if (s->oas == OAS_MODE_48) {
         s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48);
     }
 
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index e7fec7a69e..5b85247606 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1981,7 +1981,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
             error_setg(errp, "ats can only be enabled if accel=on");
             return false;
         }
-        if (s->oas != SMMU_OAS_44BIT) {
+        if (s->oas > OAS_MODE_44) {
             error_setg(errp, "OAS must be 44 bits when accel=off");
             return false;
         }
@@ -2014,7 +2014,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
         return false;
     }
 
-    if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
+    if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {
         error_setg(errp, "OAS can only be set to 44 or 48 bits");
         return false;
     }
@@ -2145,7 +2145,7 @@ static const Property smmuv3_properties[] = {
     /* RIL can be turned off for accel cases */
     DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON),
     DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF),
-    DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
+    DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44),
     DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize,
                               SSID_SIZE_MODE_0),
 };
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index ddf472493d..82f18eb090 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -72,7 +72,7 @@ struct SMMUv3State {
     Error *migration_blocker;
     OnOffAuto ril;
     OnOffAuto ats;
-    uint8_t oas;
+    OasMode oas;
     SsidSizeMode ssidsize;
 };
 
-- 
2.43.0

[PATCH v3 8/8] qemu-options.hx: Document arm-smmuv3 device's accel properties

[Nathan Chen]

From: Nathan Chen <nathanc@nvidia.com>

Document arm-smmuv3 properties for setting HW-acceleration,
Range Invalidation, and Address Translation Services support, as
well as setting Output Address size and Substream ID size.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 qemu-options.hx | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/qemu-options.hx b/qemu-options.hx
index 69e5a874c1..0ba8322695 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1279,13 +1279,46 @@ SRST
     ``aw-bits=val`` (val between 32 and 64, default depends on machine)
         This decides the address width of the IOVA address space.
 
-``-device arm-smmuv3,primary-bus=id``
+``-device arm-smmuv3,primary-bus=id[,option=...]``
     This is only supported by ``-machine virt`` (ARM).
 
     ``primary-bus=id``
         Accepts either the default root complex (pcie.0) or a
         pxb-pcie based root complex.
 
+    ``accel=on|off`` (default: off)
+        Enables guest to leverage host SMMUv3 features for acceleration.
+        Enabling accel configures the host SMMUv3 in nested mode to support
+        vfio-pci passthrough.
+
+    ``ril=on|off`` (default: on)
+        Support for Range Invalidation, which allows the SMMUv3 driver to
+        invalidate TLB entries for a range of IOVAs at once instead of issuing
+        separate commands to invalidate each page. Must match with host SMMUv3
+        Range Invalidation support. Only applicable when accel=on. Setting
+        'auto' is currently not supported.
+
+    ``ats=on|off`` (default: off)
+        Support for Address Translation Services, which enables PCIe devices to
+        cache address translations in their local TLB and reduce latency. Host
+        SMMUv3 must support ATS in order to enable this feature for the vIOMMU.
+        Only applicable when accel=on. Setting 'auto' is currently not
+        supported.
+
+    ``oas=val`` (supported values are 44 and 48. default: 44)
+        Sets the Output Address Size in bits. The value set here must be less
+        than or equal to the host SMMUv3's supported OAS, so that the
+        intermediate physical addresses (IPA) consumed by host SMMU for stage-2
+        translation do not exceed the host's max supported IPA size.
+        Only applicable when accel=on. Setting 'auto' is currently not
+        supported.
+
+    ``ssidsize=val`` (val between 0 and 20. default: 0)
+        Sets the Substream ID size in bits. When set to a non-zero value,
+        PASID capability is advertised to the vIOMMU and accelerated use cases
+        such as Shared Virtual Addressing (SVA) are supported. Only applicable
+        when accel=on. Setting 'auto' is currently not supported.
+
 ``-device amd-iommu[,option=...]``
     Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU).
     Only available with ``-machine q35``, it supports the following options:
-- 
2.43.0

RE: [PATCH v3 1/8] hw/arm/smmuv3-accel: Check ATS compatibility between host and guest

[Shameer Kolothum Thodi]

> -----Original Message-----
> From: Nathan Chen <nathanc@nvidia.com>
> Sent: 17 March 2026 18:38
> To: qemu-devel@nongnu.org; qemu-arm@nongnu.org
> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
> <peter.maydell@linaro.org>; Shannon Zhao <shannon.zhaosl@gmail.com>;
> Michael S . Tsirkin <mst@redhat.com>; Igor Mammedov
> <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Daniel P . Berrangé <berrange@redhat.com>; Eric
> Blake <eblake@redhat.com>; Markus Armbruster <armbru@redhat.com>;
> Shameer Kolothum Thodi <skolothumtho@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>; Nathan Chen
> <nathanc@nvidia.com>
> Subject: [PATCH v3 1/8] hw/arm/smmuv3-accel: Check ATS compatibility
> between host and guest
> 
> From: Nathan Chen <nathanc@nvidia.com>
> 
> Compare the host SMMUv3 ATS support bit with the guest SMMUv3 ATS
> support bit in IDR0 and fail the compatibility check if ATS support is opted as
> enabled on the guest SMMUv3 when it is not supported on host SMMUv3.
> 
> Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS")
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3-accel.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index
> 17306cd04b..2bb142c47f 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -101,6 +101,12 @@
> smmuv3_accel_check_hw_compatible(SMMUv3State *s,
>                     smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS)));
>          return false;
>      }
> +    /* Check ATS value opted is compatible with Host SMMUv3 */
> +    if (FIELD_EX32(info->idr[0], IDR0, ATS) <
> +                FIELD_EX32(s->idr[0], IDR0, ATS)) {
> +        error_setg(errp, "Host SMMUv3 doesn't support Address Translation
> Services");
> +        return false;
> +    }

Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>

Thanks,
Shameer

RE: [PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to OnOffAuto

[Shameer Kolothum Thodi]

> -----Original Message-----
> From: Nathan Chen <nathanc@nvidia.com>
> Sent: 17 March 2026 18:38
> To: qemu-devel@nongnu.org; qemu-arm@nongnu.org
> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
> <peter.maydell@linaro.org>; Shannon Zhao <shannon.zhaosl@gmail.com>;
> Michael S . Tsirkin <mst@redhat.com>; Igor Mammedov
> <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Daniel P . Berrangé <berrange@redhat.com>; Eric
> Blake <eblake@redhat.com>; Markus Armbruster <armbru@redhat.com>;
> Shameer Kolothum Thodi <skolothumtho@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>; Nathan Chen
> <nathanc@nvidia.com>
> Subject: [PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to
> OnOffAuto
> 
> From: Nathan Chen <nathanc@nvidia.com>
> 
> Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto'
> value is not implemented, as this commit is meant to set the property
> to the correct type and avoid breaking JSON/QMP when the auto mode is
> introduced. A future patch will implement resolution of the 'auto'
> value to match the host SMMUv3 ATS support.
> 
> Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS")
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3-accel.c    |  6 ++++--
>  hw/arm/smmuv3.c          | 14 ++++++++++++--
>  hw/arm/virt-acpi-build.c |  2 +-
>  include/hw/arm/smmuv3.h  |  4 +++-
>  4 files changed, 20 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index 2bb142c47f..621ac531a5 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -826,8 +826,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
>      /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */
>      s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril);
> 
> -    /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */
> -    s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, s->ats);
> +    /* Only override ATS if user explicitly set ON */
> +    if (s->ats == ON_OFF_AUTO_ON) {
> +        s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1);
> +    }

Nit: I think we can keep the original comment.

> 
>      /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */
>      if (s->oas == SMMU_OAS_48BIT) {
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 068108e49b..3dead0bcd3 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s)
>      smmuv3_accel_idr_override(s);
>  }
> 
> +bool smmuv3_ats_enabled(SMMUv3State *s)
> +{
> +    return FIELD_EX32(s->idr[0], IDR0, ATS);
> +}
> +
>  static void smmuv3_reset(SMMUv3State *s)
>  {
>      s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
> @@ -1971,7 +1976,7 @@ static bool
> smmu_validate_property(SMMUv3State *s, Error **errp)
>              error_setg(errp, "ril can only be disabled if accel=on");
>              return false;
>          }
> -        if (s->ats) {
> +        if (s->ats == ON_OFF_AUTO_ON) {
>              error_setg(errp, "ats can only be enabled if accel=on");
>              return false;
>          }
> @@ -1993,6 +1998,11 @@ static bool
> smmu_validate_property(SMMUv3State *s, Error **errp)
>          return false;
>      }
> 
> +    if (s->ats == ON_OFF_AUTO_AUTO) {
> +        error_setg(errp, "ats cannot be set to auto");
> +        return false;
> +    }
 Nit: Is "ats auto mode not supported" better? 

Also, should we do this before the if (!s->accel)  check above?
Otherwise, I think it will carry on for non-accel smmuv3 cases like,

-device arm-smmuv3,primary-bus=pcie.1,accel=off,ats=auto

I think this applies to other properties in this series as well.

>      if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
>          error_setg(errp, "OAS can only be set to 44 or 48 bits");
>          return false;
> @@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] = {
>      DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0),
>      /* RIL can be turned off for accel cases */
>      DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true),
> -    DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false),
> +    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats,
> ON_OFF_AUTO_OFF),

I think we should update the description in object_class_property_set_description
to mention auto not supported.

Thanks,
Shameer

>      DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
>      DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0),
>  };
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 719d2f994e..591cfc993c 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void
> *opaque)
> 
>      bus = PCI_BUS(object_property_get_link(obj, "primary-bus",
> &error_abort));
>      sdev.accel = object_property_get_bool(obj, "accel", &error_abort);
> -    sdev.ats = object_property_get_bool(obj, "ats", &error_abort);
> +    sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));
>      pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
>      sbdev = SYS_BUS_DEVICE(obj);
>      sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
> diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
> index 26b2fc42fd..ce51a5b9b4 100644
> --- a/include/hw/arm/smmuv3.h
> +++ b/include/hw/arm/smmuv3.h
> @@ -70,7 +70,7 @@ struct SMMUv3State {
>      uint64_t msi_gpa;
>      Error *migration_blocker;
>      bool ril;
> -    bool ats;
> +    OnOffAuto ats;
>      uint8_t oas;
>      uint8_t ssidsize;
>  };
> @@ -91,6 +91,8 @@ struct SMMUv3Class {
>      ResettablePhases parent_phases;
>  };
> 
> +bool smmuv3_ats_enabled(struct SMMUv3State *s);
> +
>  #define TYPE_ARM_SMMUV3   "arm-smmuv3"
>  OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
> 
> --
> 2.43.0

RE: [PATCH v3 5/8] hw/arm/smmuv3-accel: Change SSIDSIZE property to SsidSizeMode

[Shameer Kolothum Thodi]

> -----Original Message-----
> From: Nathan Chen <nathanc@nvidia.com>
> Sent: 17 March 2026 18:38
> To: qemu-devel@nongnu.org; qemu-arm@nongnu.org
> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
> <peter.maydell@linaro.org>; Shannon Zhao <shannon.zhaosl@gmail.com>;
> Michael S . Tsirkin <mst@redhat.com>; Igor Mammedov
> <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Daniel P . Berrangé <berrange@redhat.com>; Eric
> Blake <eblake@redhat.com>; Markus Armbruster <armbru@redhat.com>;
> Shameer Kolothum Thodi <skolothumtho@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>; Nathan Chen
> <nathanc@nvidia.com>
> Subject: [PATCH v3 5/8] hw/arm/smmuv3-accel: Change SSIDSIZE property to
> SsidSizeMode
> 
> From: Nathan Chen <nathanc@nvidia.com>
> 
> Change accel SMMUv3 SSIDSIZE property from uint8_t to SsidSizeMode.
> The 'auto' value is not implemented, as this commit is meant to set the
> property to the correct type and avoid breaking JSON/QMP when the auto
> mode is introduced. A future patch will implement resolution of 'auto'
> value to match the host SMMUv3 SSIDSIZE value.
> 
> Fixes: b8c6f8a69d27 ("hw/arm/smmuv3-accel: Make SubstreamID support
> configurable")
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3-accel.c   | 23 +++++++++++++++++++++--
>  hw/arm/smmuv3.c         | 18 ++++++++++--------
>  include/hw/arm/smmuv3.h |  3 ++-
>  3 files changed, 33 insertions(+), 11 deletions(-)
> 
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index ddd927fa80..c90fa9f5bb 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -802,7 +802,7 @@ static uint64_t
> smmuv3_accel_get_viommu_flags(void *opaque)
>      SMMUState *bs = opaque;
>      SMMUv3State *s = ARM_SMMUV3(bs);
> 
> -    if (s->ssidsize) {
> +    if (s->ssidsize > SSID_SIZE_MODE_0) {
>          flags |= VIOMMU_FLAG_PASID_SUPPORTED;
>      }
>      return flags;
> @@ -817,6 +817,22 @@ static const PCIIOMMUOps smmuv3_accel_ops = {
>      .get_msi_direct_gpa = smmuv3_accel_get_msi_gpa,
>  };
> 
> +/*
> + * This returns the value of a SsidSizeMode value offset by 1 to
> + * account for the enum values offset by 1 from actual values.
> + *
> + * SSID_SIZE_MODE_0 = 1, SSID_SIZE_MODE_1 = 2, etc. so return 0
> + * if SSID_SIZE_MODE_0 is passed as input, return 1 if
> + * SSID_SIZE_MODE_1 is passed as input, etc.
> + */
> +static uint8_t ssidsize_mode_to_value(SsidSizeMode mode)
> +{
> +    if (mode == SSID_SIZE_MODE_AUTO) {
> +        return 0;
> +    }
> +    return mode - 1;
> +}
> +
>  void smmuv3_accel_idr_override(SMMUv3State *s)
>  {
>      if (!s->accel) {
> @@ -842,7 +858,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
>       * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if
> user
>       * has enabled it.
>       */
> -    s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize);
> +    if (s->ssidsize > SSID_SIZE_MODE_0) {
> +        s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,
> +                               ssidsize_mode_to_value(s->ssidsize));
> +    }
>  }
> 
>  /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding
> HWPT */
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 40d6aca83e..e7fec7a69e 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -20,6 +20,7 @@
>  #include "qemu/bitops.h"
>  #include "hw/core/irq.h"
>  #include "hw/core/sysbus.h"
> +#include "hw/core/qdev-properties-system.h"
>  #include "migration/blocker.h"
>  #include "migration/vmstate.h"
>  #include "hw/core/qdev-properties.h"
> @@ -625,7 +626,7 @@ static int decode_ste(SMMUv3State *s,
> SMMUTransCfg *cfg,
>      }
> 
>      /* Multiple context descriptors require SubstreamID support */
> -    if (!s->ssidsize && STE_S1CDMAX(ste) != 0) {
> +    if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {
>          qemu_log_mask(LOG_UNIMP,
>                  "SMMUv3: multiple S1 context descriptors require SubstreamID
> support. "
>                  "Configure ssidsize > 0 (requires accel=on)\n");
> @@ -1984,7 +1985,7 @@ static bool
> smmu_validate_property(SMMUv3State *s, Error **errp)
>              error_setg(errp, "OAS must be 44 bits when accel=off");
>              return false;
>          }
> -        if (s->ssidsize) {
> +        if (s->ssidsize > SSID_SIZE_MODE_0) {
>              error_setg(errp, "ssidsize can only be set if accel=on");
>              return false;
>          }
> @@ -2008,13 +2009,13 @@ static bool
> smmu_validate_property(SMMUv3State *s, Error **errp)
>          return false;
>      }
> 
> -    if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
> -        error_setg(errp, "OAS can only be set to 44 or 48 bits");
> +    if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
> +        error_setg(errp, "ssidsize cannot be set to auto");
>          return false;
>      }
> -    if (s->ssidsize > SMMU_SSID_MAX_BITS) {
> -        error_setg(errp, "ssidsize must be in the range 0 to %d",
> -                   SMMU_SSID_MAX_BITS);

I think we can now get rid of the "#define SMMU_SSID_MAX_BITS"
as I don't think it is used anywhere else and SsidSizeMode won't
accept anything > 20. Right?

Thanks,
Shameer

> +
> +    if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
> +        error_setg(errp, "OAS can only be set to 44 or 48 bits");
>          return false;
>      }
> 
> @@ -2145,7 +2146,8 @@ static const Property smmuv3_properties[] = {
>      DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril,
> ON_OFF_AUTO_ON),
>      DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats,
> ON_OFF_AUTO_OFF),
>      DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
> -    DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0),
> +    DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize,
> +                              SSID_SIZE_MODE_0),
>  };
> 
>  static void smmuv3_instance_init(Object *obj)
> diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
> index c35e599bbc..ddf472493d 100644
> --- a/include/hw/arm/smmuv3.h
> +++ b/include/hw/arm/smmuv3.h
> @@ -21,6 +21,7 @@
> 
>  #include "hw/arm/smmu-common.h"
>  #include "qom/object.h"
> +#include "qapi/qapi-types-misc-arm.h"
> 
>  #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-
> memory-region"
> 
> @@ -72,7 +73,7 @@ struct SMMUv3State {
>      OnOffAuto ril;
>      OnOffAuto ats;
>      uint8_t oas;
> -    uint8_t ssidsize;
> +    SsidSizeMode ssidsize;
>  };
> 
>  typedef enum {
> --
> 2.43.0

RE: [PATCH v3 7/8] hw/arm/smmuv3-accel: Change OAS property to OasMode

[Shameer Kolothum Thodi]

> -----Original Message-----
> From: Nathan Chen <nathanc@nvidia.com>
> Sent: 17 March 2026 18:38
> To: qemu-devel@nongnu.org; qemu-arm@nongnu.org
> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
> <peter.maydell@linaro.org>; Shannon Zhao <shannon.zhaosl@gmail.com>;
> Michael S . Tsirkin <mst@redhat.com>; Igor Mammedov
> <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Daniel P . Berrangé <berrange@redhat.com>; Eric
> Blake <eblake@redhat.com>; Markus Armbruster <armbru@redhat.com>;
> Shameer Kolothum Thodi <skolothumtho@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>; Nathan Chen
> <nathanc@nvidia.com>
> Subject: [PATCH v3 7/8] hw/arm/smmuv3-accel: Change OAS property to
> OasMode
> 
> From: Nathan Chen <nathanc@nvidia.com>
> 
> Change accel SMMUv3 OAS property from uint8_t to OasMode. The
> 'auto' value is not implemented, as this commit is meant to
> set the property to the correct type and avoid breaking JSON/QMP
> when the auto mode is introduced. A future patch will implement
> resolution of 'auto' value to match the host SMMUv3 OAS value.
> 
> Fixes: a015ac990fd3 ("hw/arm/smmuv3-accel: Add property to specify OAS
> bits")
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3-accel.c   | 2 +-
>  hw/arm/smmuv3.c         | 6 +++---
>  include/hw/arm/smmuv3.h | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index c90fa9f5bb..08a4e2a1c8 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -850,7 +850,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
>      }
> 
>      /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */
> -    if (s->oas == SMMU_OAS_48BIT) {
> +    if (s->oas == OAS_MODE_48) {
>          s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48);
>      }
> 
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index e7fec7a69e..5b85247606 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -1981,7 +1981,7 @@ static bool
> smmu_validate_property(SMMUv3State *s, Error **errp)
>              error_setg(errp, "ats can only be enabled if accel=on");
>              return false;
>          }
> -        if (s->oas != SMMU_OAS_44BIT) {
> +        if (s->oas > OAS_MODE_44) {
>              error_setg(errp, "OAS must be 44 bits when accel=off");
>              return false;
>          }
> @@ -2014,7 +2014,7 @@ static bool
> smmu_validate_property(SMMUv3State *s, Error **errp)
>          return false;
>      }
> 
> -    if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
> +    if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {

Same here. We can get rid of SMMU_OAS_44BIT/_48BIT defines.

Thanks,
Shameer

>          error_setg(errp, "OAS can only be set to 44 or 48 bits");
>          return false;
>      }
> @@ -2145,7 +2145,7 @@ static const Property smmuv3_properties[] = {
>      /* RIL can be turned off for accel cases */
>      DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril,
> ON_OFF_AUTO_ON),
>      DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats,
> ON_OFF_AUTO_OFF),
> -    DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
> +    DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44),
>      DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize,
>                                SSID_SIZE_MODE_0),
>  };
> diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
> index ddf472493d..82f18eb090 100644
> --- a/include/hw/arm/smmuv3.h
> +++ b/include/hw/arm/smmuv3.h
> @@ -72,7 +72,7 @@ struct SMMUv3State {
>      Error *migration_blocker;
>      OnOffAuto ril;
>      OnOffAuto ats;
> -    uint8_t oas;
> +    OasMode oas;
>      SsidSizeMode ssidsize;
>  };
> 
> --
> 2.43.0

RE: [PATCH v3 8/8] qemu-options.hx: Document arm-smmuv3 device's accel properties

[Shameer Kolothum Thodi]

> -----Original Message-----
> From: Nathan Chen <nathanc@nvidia.com>
> Sent: 17 March 2026 18:38
> To: qemu-devel@nongnu.org; qemu-arm@nongnu.org
> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
> <peter.maydell@linaro.org>; Shannon Zhao <shannon.zhaosl@gmail.com>;
> Michael S . Tsirkin <mst@redhat.com>; Igor Mammedov
> <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Daniel P . Berrangé <berrange@redhat.com>; Eric
> Blake <eblake@redhat.com>; Markus Armbruster <armbru@redhat.com>;
> Shameer Kolothum Thodi <skolothumtho@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>; Nathan Chen
> <nathanc@nvidia.com>
> Subject: [PATCH v3 8/8] qemu-options.hx: Document arm-smmuv3 device's
> accel properties
> 
> From: Nathan Chen <nathanc@nvidia.com>
> 
> Document arm-smmuv3 properties for setting HW-acceleration, Range
> Invalidation, and Address Translation Services support, as well as setting
> Output Address size and Substream ID size.
> 
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  qemu-options.hx | 35 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 34 insertions(+), 1 deletion(-)
> 
> diff --git a/qemu-options.hx b/qemu-options.hx index
> 69e5a874c1..0ba8322695 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -1279,13 +1279,46 @@ SRST
>      ``aw-bits=val`` (val between 32 and 64, default depends on machine)
>          This decides the address width of the IOVA address space.
> 
> -``-device arm-smmuv3,primary-bus=id``
> +``-device arm-smmuv3,primary-bus=id[,option=...]``
>      This is only supported by ``-machine virt`` (ARM).
> 
>      ``primary-bus=id``
>          Accepts either the default root complex (pcie.0) or a
>          pxb-pcie based root complex.
> 
> +    ``accel=on|off`` (default: off)
> +        Enables guest to leverage host SMMUv3 features for acceleration.
> +        Enabling accel configures the host SMMUv3 in nested mode to support
> +        vfio-pci passthrough.

Nit: Instead of repeating for all options below, may be we can add something like
below here:
             The following options are available when accel=on.
             Note: 'auto' mode is not currently supported.

> +
> +    ``ril=on|off`` (default: on)
> +        Support for Range Invalidation, which allows the SMMUv3 driver to
> +        invalidate TLB entries for a range of IOVAs at once instead of issuing
> +        separate commands to invalidate each page. Must match with host
> SMMUv3
> +        Range Invalidation support. Only applicable when accel=on. Setting
> +        'auto' is currently not supported.
> +
> +    ``ats=on|off`` (default: off)
> +        Support for Address Translation Services, which enables PCIe devices to
> +        cache address translations in their local TLB and reduce latency. Host
> +        SMMUv3 must support ATS in order to enable this feature for the
> vIOMMU.
> +        Only applicable when accel=on. Setting 'auto' is currently not
> +        supported.
> +
> +    ``oas=val`` (supported values are 44 and 48. default: 44)
> +        Sets the Output Address Size in bits. The value set here must be less
> +        than or equal to the host SMMUv3's supported OAS, so that the
> +        intermediate physical addresses (IPA) consumed by host SMMU for
> stage-2
> +        translation do not exceed the host's max supported IPA size.
> +        Only applicable when accel=on. Setting 'auto' is currently not
> +        supported.
> +
> +    ``ssidsize=val`` (val between 0 and 20. default: 0)
> +        Sets the Substream ID size in bits. When set to a non-zero value,
> +        PASID capability is advertised to the vIOMMU and accelerated use cases
> +        such as Shared Virtual Addressing (SVA) are supported. Only applicable
> +        when accel=on. Setting 'auto' is currently not supported.
> +

Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>

Thanks,
Shameer

Re: [PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to OnOffAuto

[Eric Auger]

On 3/18/26 10:31 AM, Shameer Kolothum Thodi wrote:
>
>> -----Original Message-----
>> From: Nathan Chen <nathanc@nvidia.com>
>> Sent: 17 March 2026 18:38
>> To: qemu-devel@nongnu.org; qemu-arm@nongnu.org
>> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Shannon Zhao <shannon.zhaosl@gmail.com>;
>> Michael S . Tsirkin <mst@redhat.com>; Igor Mammedov
>> <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo Bonzini
>> <pbonzini@redhat.com>; Daniel P . Berrangé <berrange@redhat.com>; Eric
>> Blake <eblake@redhat.com>; Markus Armbruster <armbru@redhat.com>;
>> Shameer Kolothum Thodi <skolothumtho@nvidia.com>; Matt Ochs
>> <mochs@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>; Nathan Chen
>> <nathanc@nvidia.com>
>> Subject: [PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to
>> OnOffAuto
>>
>> From: Nathan Chen <nathanc@nvidia.com>
>>
>> Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto'
>> value is not implemented, as this commit is meant to set the property
>> to the correct type and avoid breaking JSON/QMP when the auto mode is
>> introduced. A future patch will implement resolution of the 'auto'
>> value to match the host SMMUv3 ATS support.
>>
>> Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS")
>> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
>> ---
>>  hw/arm/smmuv3-accel.c    |  6 ++++--
>>  hw/arm/smmuv3.c          | 14 ++++++++++++--
>>  hw/arm/virt-acpi-build.c |  2 +-
>>  include/hw/arm/smmuv3.h  |  4 +++-
>>  4 files changed, 20 insertions(+), 6 deletions(-)
>>
>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
>> index 2bb142c47f..621ac531a5 100644
>> --- a/hw/arm/smmuv3-accel.c
>> +++ b/hw/arm/smmuv3-accel.c
>> @@ -826,8 +826,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
>>      /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */
>>      s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril);
>>
>> -    /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */
>> -    s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, s->ats);
>> +    /* Only override ATS if user explicitly set ON */
>> +    if (s->ats == ON_OFF_AUTO_ON) {
>> +        s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1);
>> +    }
> Nit: I think we can keep the original comment.
>
>>      /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */
>>      if (s->oas == SMMU_OAS_48BIT) {
>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
>> index 068108e49b..3dead0bcd3 100644
>> --- a/hw/arm/smmuv3.c
>> +++ b/hw/arm/smmuv3.c
>> @@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s)
>>      smmuv3_accel_idr_override(s);
>>  }
>>
>> +bool smmuv3_ats_enabled(SMMUv3State *s)
>> +{
>> +    return FIELD_EX32(s->idr[0], IDR0, ATS);
>> +}
>> +
>>  static void smmuv3_reset(SMMUv3State *s)
>>  {
>>      s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
>> @@ -1971,7 +1976,7 @@ static bool
>> smmu_validate_property(SMMUv3State *s, Error **errp)
>>              error_setg(errp, "ril can only be disabled if accel=on");
>>              return false;
>>          }
>> -        if (s->ats) {
>> +        if (s->ats == ON_OFF_AUTO_ON) {
>>              error_setg(errp, "ats can only be enabled if accel=on");
>>              return false;
>>          }
>> @@ -1993,6 +1998,11 @@ static bool
>> smmu_validate_property(SMMUv3State *s, Error **errp)
>>          return false;
>>      }
>>
>> +    if (s->ats == ON_OFF_AUTO_AUTO) {
>> +        error_setg(errp, "ats cannot be set to auto");
>> +        return false;
>> +    }
>  Nit: Is "ats auto mode not supported" better? 
>
> Also, should we do this before the if (!s->accel)  check above?
> Otherwise, I think it will carry on for non-accel smmuv3 cases like,
>
> -device arm-smmuv3,primary-bus=pcie.1,accel=off,ats=auto
>
> I think this applies to other properties in this series as well.
>
>>      if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
>>          error_setg(errp, "OAS can only be set to 44 or 48 bits");
>>          return false;
>> @@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] = {
>>      DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0),
>>      /* RIL can be turned off for accel cases */
>>      DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true),
>> -    DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false),
>> +    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats,
>> ON_OFF_AUTO_OFF),
> I think we should update the description in object_class_property_set_description
> to mention auto not supported.

I agree with Shameer wrt all above comments

Eric
>
> Thanks,
> Shameer
>
>>      DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44),
>>      DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0),
>>  };
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index 719d2f994e..591cfc993c 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void
>> *opaque)
>>
>>      bus = PCI_BUS(object_property_get_link(obj, "primary-bus",
>> &error_abort));
>>      sdev.accel = object_property_get_bool(obj, "accel", &error_abort);
>> -    sdev.ats = object_property_get_bool(obj, "ats", &error_abort);
>> +    sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));
>>      pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
>>      sbdev = SYS_BUS_DEVICE(obj);
>>      sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
>> diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
>> index 26b2fc42fd..ce51a5b9b4 100644
>> --- a/include/hw/arm/smmuv3.h
>> +++ b/include/hw/arm/smmuv3.h
>> @@ -70,7 +70,7 @@ struct SMMUv3State {
>>      uint64_t msi_gpa;
>>      Error *migration_blocker;
>>      bool ril;
>> -    bool ats;
>> +    OnOffAuto ats;
>>      uint8_t oas;
>>      uint8_t ssidsize;
>>  };
>> @@ -91,6 +91,8 @@ struct SMMUv3Class {
>>      ResettablePhases parent_phases;
>>  };
>>
>> +bool smmuv3_ats_enabled(struct SMMUv3State *s);
>> +
>>  #define TYPE_ARM_SMMUV3   "arm-smmuv3"
>>  OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
>>
>> --
>> 2.43.0

Re: [PATCH for-11.0 v3 0/8] hw/arm/smmuv3-accel: Support AUTO properties

[Eric Auger]

Hi Nathan,

On 3/17/26 7:37 PM, Nathan Chen wrote:
> Hi,
>
> This is a follow-up to the previous series [0] that introduces support
> for specifying 'auto' for arm-smmuv3 accelerated mode's ATS, RIL,
> SSIDSIZE, and OAS feature properties.
>
> In QEMU 11.0 we introduced new options for vSMMU [1], but feedback received
> when starting the integration of layered products shows the need for
> auto/host-retrieved values. To avoid breaking JSON/QMP compat, we want
> to fix the option types so that they can later support the auto mode. At
> the moment the auto mode is not supported though.
>
> A future series will introduce support for resolving the 'auto' values
> based on host SMMUv3 IDR values, as well as setting per-device ATS
> capability.
>
> A complete branch can be found here:
> https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-v3
>
> Please take a look and let me know your feedback.
>
> Thanks,
> Nathan
>
> Changes from v2:
> - Enforce 'auto' value not being supported for HW-accel SMMUv3 props
> - Revise docs to mention auto is not supported and these properties
>   are only applicable when accel=on.
> - Only override non-defaults in smmuv3_accel_idr_override()
> - Remove check for SSIDSIZE AUTO in smmuv3_accel_idr_override() as
>   smmu_validate_property() checks for AUTO beforehand
> - Consolidate comments for ssidsize_mode_to_value()
> - Include Fixes tags in commit descriptions
> - Include R-by tags from v2
>
> Changes from RFCv1:
> - Remove changes that resolve the 'auto' values based on host SMMUv3
> - Restore defaults values for RIL, OAS, SSIDSIZE, and ATS
> - Update OasMode to accept all OAS sizes instead of only auto, 44, and
>   48
> - Include comment in SsidSizeMode schema clarifying enum value
>   ordering
> - Replace ats-enabled prop with a helper that accepts the dynamic
>   casted TYPE_ARM_SMMUV3 object
> - Separate out guest vs. host ATS check in
>   smmuv3_accel_check_hw_compatible() to a different commit
> - Document accel, RIL, OAS, SSIDSIZE, and ATS properties in
>   qemu-options.hx
>
> Testing:
> Basic sanity testing was performed on an NVIDIA Grace platform with GPU
> device assignment and running CUDA test apps on the guest. Additional
> testing and feedback are welcome.

Feel free to add my
Tested-by: Eric Auger <eric.auger@redhat.com>

Eric
>
> [0] https://lore.kernel.org/qemu-devel/20260312210328.2016191-1-nathanc@nvidia.com/
> [1] https://lore.kernel.org/all/20260126104342.253965-1-skolothumtho@nvidia.com/
>
> Nathan Chen (8):
>   hw/arm/smmuv3-accel: Check ATS compatibility between host and guest
>   hw/arm/smmuv3-accel: Change ATS property to OnOffAuto
>   hw/arm/smmuv3-accel: Change RIL property to OnOffAuto
>   qdev: Add a SsidSizeMode property
>   hw/arm/smmuv3-accel: Change SSIDSIZE property to SsidSizeMode
>   qdev: Add an OasMode property
>   hw/arm/smmuv3-accel: Change OAS property to OasMode
>   qemu-options.hx: Document arm-smmuv3 device's accel properties
>
>  hw/arm/smmuv3-accel.c                    | 43 ++++++++++++++++++----
>  hw/arm/smmuv3.c                          | 45 ++++++++++++++++--------
>  hw/arm/virt-acpi-build.c                 |  2 +-
>  hw/core/qdev-properties-system.c         | 27 ++++++++++++++
>  include/hw/arm/smmuv3.h                  | 11 +++---
>  include/hw/core/qdev-properties-system.h |  6 ++++
>  qapi/misc-arm.json                       | 44 +++++++++++++++++++++++
>  qapi/pragma.json                         |  1 +
>  qemu-options.hx                          | 35 +++++++++++++++++-
>  9 files changed, 187 insertions(+), 27 deletions(-)
>

Re: [PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to OnOffAuto

[Nathan Chen]

On 3/18/2026 6:38 AM, Eric Auger wrote:
> 
> On 3/18/26 10:31 AM, Shameer Kolothum Thodi wrote:
>>> -----Original Message-----
>>> From: Nathan Chen<nathanc@nvidia.com>
>>> Sent: 17 March 2026 18:38
>>> To:qemu-devel@nongnu.org;qemu-arm@nongnu.org
>>> Cc: Eric Auger<eric.auger@redhat.com>; Peter Maydell
>>> <peter.maydell@linaro.org>; Shannon Zhao<shannon.zhaosl@gmail.com>;
>>> Michael S . Tsirkin<mst@redhat.com>; Igor Mammedov
>>> <imammedo@redhat.com>; Ani Sinha<anisinha@redhat.com>; Paolo Bonzini
>>> <pbonzini@redhat.com>; Daniel P . Berrangé<berrange@redhat.com>; Eric
>>> Blake<eblake@redhat.com>; Markus Armbruster<armbru@redhat.com>;
>>> Shameer Kolothum Thodi<skolothumtho@nvidia.com>; Matt Ochs
>>> <mochs@nvidia.com>; Nicolin Chen<nicolinc@nvidia.com>; Nathan Chen
>>> <nathanc@nvidia.com>
>>> Subject: [PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to
>>> OnOffAuto
>>>
>>> From: Nathan Chen<nathanc@nvidia.com>
>>>
>>> Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto'
>>> value is not implemented, as this commit is meant to set the property
>>> to the correct type and avoid breaking JSON/QMP when the auto mode is
>>> introduced. A future patch will implement resolution of the 'auto'
>>> value to match the host SMMUv3 ATS support.
>>>
>>> Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS")
>>> Signed-off-by: Nathan Chen<nathanc@nvidia.com>
>>> ---
>>>   hw/arm/smmuv3-accel.c    |  6 ++++--
>>>   hw/arm/smmuv3.c          | 14 ++++++++++++--
>>>   hw/arm/virt-acpi-build.c |  2 +-
>>>   include/hw/arm/smmuv3.h  |  4 +++-
>>>   4 files changed, 20 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
>>> index 2bb142c47f..621ac531a5 100644
>>> --- a/hw/arm/smmuv3-accel.c
>>> +++ b/hw/arm/smmuv3-accel.c
>>> @@ -826,8 +826,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
>>>       /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */
>>>       s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril);
>>>
>>> -    /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */
>>> -    s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, s->ats);
>>> +    /* Only override ATS if user explicitly set ON */
>>> +    if (s->ats == ON_OFF_AUTO_ON) {
>>> +        s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1);
>>> +    }
>> Nit: I think we can keep the original comment.
>>
>>>       /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */
>>>       if (s->oas == SMMU_OAS_48BIT) {
>>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
>>> index 068108e49b..3dead0bcd3 100644
>>> --- a/hw/arm/smmuv3.c
>>> +++ b/hw/arm/smmuv3.c
>>> @@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s)
>>>       smmuv3_accel_idr_override(s);
>>>   }
>>>
>>> +bool smmuv3_ats_enabled(SMMUv3State *s)
>>> +{
>>> +    return FIELD_EX32(s->idr[0], IDR0, ATS);
>>> +}
>>> +
>>>   static void smmuv3_reset(SMMUv3State *s)
>>>   {
>>>       s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
>>> @@ -1971,7 +1976,7 @@ static bool
>>> smmu_validate_property(SMMUv3State *s, Error **errp)
>>>               error_setg(errp, "ril can only be disabled if accel=on");
>>>               return false;
>>>           }
>>> -        if (s->ats) {
>>> +        if (s->ats == ON_OFF_AUTO_ON) {
>>>               error_setg(errp, "ats can only be enabled if accel=on");
>>>               return false;
>>>           }
>>> @@ -1993,6 +1998,11 @@ static bool
>>> smmu_validate_property(SMMUv3State *s, Error **errp)
>>>           return false;
>>>       }
>>>
>>> +    if (s->ats == ON_OFF_AUTO_AUTO) {
>>> +        error_setg(errp, "ats cannot be set to auto");
>>> +        return false;
>>> +    }
>>   Nit: Is "ats auto mode not supported" better?
>>
>> Also, should we do this before the if (!s->accel)  check above?
>> Otherwise, I think it will carry on for non-accel smmuv3 cases like,
>>
>> -device arm-smmuv3,primary-bus=pcie.1,accel=off,ats=auto
>>
>> I think this applies to other properties in this series as well.
>>
>>>       if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
>>>           error_setg(errp, "OAS can only be set to 44 or 48 bits");
>>>           return false;
>>> @@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] = {
>>>       DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0),
>>>       /* RIL can be turned off for accel cases */
>>>       DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true),
>>> -    DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false),
>>> +    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats,
>>> ON_OFF_AUTO_OFF),
>> I think we should update the description in object_class_property_set_description
>> to mention auto not supported.
> I agree with Shameer wrt all above comments

Yes, I will make these changes for the next refresh.

Thanks,
Nathan

Re: [PATCH v3 7/8] hw/arm/smmuv3-accel: Change OAS property to OasMode

[Nathan Chen]

On 3/18/2026 2:51 AM, Shameer Kolothum Thodi wrote:
> 
>> -----Original Message-----
>> From: Nathan Chen<nathanc@nvidia.com>
>> Sent: 17 March 2026 18:38
>> To:qemu-devel@nongnu.org;qemu-arm@nongnu.org
>> Cc: Eric Auger<eric.auger@redhat.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Shannon Zhao<shannon.zhaosl@gmail.com>;
>> Michael S . Tsirkin<mst@redhat.com>; Igor Mammedov
>> <imammedo@redhat.com>; Ani Sinha<anisinha@redhat.com>; Paolo Bonzini
>> <pbonzini@redhat.com>; Daniel P . Berrangé<berrange@redhat.com>; Eric
>> Blake<eblake@redhat.com>; Markus Armbruster<armbru@redhat.com>;
>> Shameer Kolothum Thodi<skolothumtho@nvidia.com>; Matt Ochs
>> <mochs@nvidia.com>; Nicolin Chen<nicolinc@nvidia.com>; Nathan Chen
>> <nathanc@nvidia.com>
>> Subject: [PATCH v3 7/8] hw/arm/smmuv3-accel: Change OAS property to
>> OasMode
>>
>> From: Nathan Chen<nathanc@nvidia.com>
>>
>> Change accel SMMUv3 OAS property from uint8_t to OasMode. The
>> 'auto' value is not implemented, as this commit is meant to
>> set the property to the correct type and avoid breaking JSON/QMP
>> when the auto mode is introduced. A future patch will implement
>> resolution of 'auto' value to match the host SMMUv3 OAS value.
>>
>> Fixes: a015ac990fd3 ("hw/arm/smmuv3-accel: Add property to specify OAS
>> bits")
>> Signed-off-by: Nathan Chen<nathanc@nvidia.com>
>> ---
>>   hw/arm/smmuv3-accel.c   | 2 +-
>>   hw/arm/smmuv3.c         | 6 +++---
>>   include/hw/arm/smmuv3.h | 2 +-
>>   3 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
>> index c90fa9f5bb..08a4e2a1c8 100644
>> --- a/hw/arm/smmuv3-accel.c
>> +++ b/hw/arm/smmuv3-accel.c
>> @@ -850,7 +850,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s)
>>       }
>>
>>       /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */
>> -    if (s->oas == SMMU_OAS_48BIT) {
>> +    if (s->oas == OAS_MODE_48) {
>>           s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48);
>>       }
>>
>> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
>> index e7fec7a69e..5b85247606 100644
>> --- a/hw/arm/smmuv3.c
>> +++ b/hw/arm/smmuv3.c
>> @@ -1981,7 +1981,7 @@ static bool
>> smmu_validate_property(SMMUv3State *s, Error **errp)
>>               error_setg(errp, "ats can only be enabled if accel=on");
>>               return false;
>>           }
>> -        if (s->oas != SMMU_OAS_44BIT) {
>> +        if (s->oas > OAS_MODE_44) {
>>               error_setg(errp, "OAS must be 44 bits when accel=off");
>>               return false;
>>           }
>> @@ -2014,7 +2014,7 @@ static bool
>> smmu_validate_property(SMMUv3State *s, Error **errp)
>>           return false;
>>       }
>>
>> -    if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {
>> +    if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {
> Same here. We can get rid of SMMU_OAS_44BIT/_48BIT defines.

Right, I will remove the SMMU_OAS_44BIT/_48BIT and SMMU_SSID_MAX_BITS 
defines.

Thanks,
Nathan

Re: [PATCH v3 8/8] qemu-options.hx: Document arm-smmuv3 device's accel properties

[Nathan Chen]

On 3/18/2026 3:36 AM, Shameer Kolothum Thodi wrote:
>> -----Original Message-----
>> From: Nathan Chen<nathanc@nvidia.com>
>> Sent: 17 March 2026 18:38
>> To:qemu-devel@nongnu.org;qemu-arm@nongnu.org
>> Cc: Eric Auger<eric.auger@redhat.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Shannon Zhao<shannon.zhaosl@gmail.com>;
>> Michael S . Tsirkin<mst@redhat.com>; Igor Mammedov
>> <imammedo@redhat.com>; Ani Sinha<anisinha@redhat.com>; Paolo Bonzini
>> <pbonzini@redhat.com>; Daniel P . Berrangé<berrange@redhat.com>; Eric
>> Blake<eblake@redhat.com>; Markus Armbruster<armbru@redhat.com>;
>> Shameer Kolothum Thodi<skolothumtho@nvidia.com>; Matt Ochs
>> <mochs@nvidia.com>; Nicolin Chen<nicolinc@nvidia.com>; Nathan Chen
>> <nathanc@nvidia.com>
>> Subject: [PATCH v3 8/8] qemu-options.hx: Document arm-smmuv3 device's
>> accel properties
>>
>> From: Nathan Chen<nathanc@nvidia.com>
>>
>> Document arm-smmuv3 properties for setting HW-acceleration, Range
>> Invalidation, and Address Translation Services support, as well as setting
>> Output Address size and Substream ID size.
>>
>> Reviewed-by: Eric Auger<eric.auger@redhat.com>
>> Signed-off-by: Nathan Chen<nathanc@nvidia.com>
>> ---
>>   qemu-options.hx | 35 ++++++++++++++++++++++++++++++++++-
>>   1 file changed, 34 insertions(+), 1 deletion(-)
>>
>> diff --git a/qemu-options.hx b/qemu-options.hx index
>> 69e5a874c1..0ba8322695 100644
>> --- a/qemu-options.hx
>> +++ b/qemu-options.hx
>> @@ -1279,13 +1279,46 @@ SRST
>>       ``aw-bits=val`` (val between 32 and 64, default depends on machine)
>>           This decides the address width of the IOVA address space.
>>
>> -``-device arm-smmuv3,primary-bus=id``
>> +``-device arm-smmuv3,primary-bus=id[,option=...]``
>>       This is only supported by ``-machine virt`` (ARM).
>>
>>       ``primary-bus=id``
>>           Accepts either the default root complex (pcie.0) or a
>>           pxb-pcie based root complex.
>>
>> +    ``accel=on|off`` (default: off)
>> +        Enables guest to leverage host SMMUv3 features for acceleration.
>> +        Enabling accel configures the host SMMUv3 in nested mode to support
>> +        vfio-pci passthrough.
> Nit: Instead of repeating for all options below, may be we can add something like
> below here:
>               The following options are available when accel=on.
>               Note: 'auto' mode is not currently supported.

Yes, I think it will be cleaner to consolidate the notes about accel=on 
and auto mode like this.

Thanks,
Nathan
> 
>> +
>> +    ``ril=on|off`` (default: on)
>> +        Support for Range Invalidation, which allows the SMMUv3 driver to
>> +        invalidate TLB entries for a range of IOVAs at once instead of issuing
>> +        separate commands to invalidate each page. Must match with host
>> SMMUv3
>> +        Range Invalidation support. Only applicable when accel=on. Setting
>> +        'auto' is currently not supported.
>> +
>> +    ``ats=on|off`` (default: off)
>> +        Support for Address Translation Services, which enables PCIe devices to
>> +        cache address translations in their local TLB and reduce latency. Host
>> +        SMMUv3 must support ATS in order to enable this feature for the
>> vIOMMU.
>> +        Only applicable when accel=on. Setting 'auto' is currently not
>> +        supported.
>> +
>> +    ``oas=val`` (supported values are 44 and 48. default: 44)
>> +        Sets the Output Address Size in bits. The value set here must be less
>> +        than or equal to the host SMMUv3's supported OAS, so that the
>> +        intermediate physical addresses (IPA) consumed by host SMMU for
>> stage-2
>> +        translation do not exceed the host's max supported IPA size.
>> +        Only applicable when accel=on. Setting 'auto' is currently not
>> +        supported.
>> +
>> +    ``ssidsize=val`` (val between 0 and 20. default: 0)
>> +        Sets the Substream ID size in bits. When set to a non-zero value,
>> +        PASID capability is advertised to the vIOMMU and accelerated use cases
>> +        such as Shared Virtual Addressing (SVA) are supported. Only applicable
>> +        when accel=on. Setting 'auto' is currently not supported.