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[118.208.214.188]) by smtp.gmail.com with ESMTPSA id p13-20020a170902a40d00b001a687c505e6sm18626178plq.232.2023.05.01.21.37.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 May 2023 21:37:22 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 02 May 2023 14:37:16 +1000 Message-Id: Cc: , , Subject: Re: [PATCH v2 1/4] ppc: spapr: cleanup cr get/store in [h_enter|spapr_exit]_nested with helpers. From: "Nicholas Piggin" To: "Harsh Prateek Bora" , X-Mailer: aerc 0.14.0 References: <20230424144712.1985425-1-harshpb@linux.ibm.com> <20230424144712.1985425-2-harshpb@linux.ibm.com> In-Reply-To: <20230424144712.1985425-2-harshpb@linux.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue Apr 25, 2023 at 12:47 AM AEST, Harsh Prateek Bora wrote: > The bits in cr reg are grouped into eight 4-bit fields represented > by env->crf[8] and the related calculations should be abstracted to > keep the calling routines simpler to read. This is a step towards > cleaning up the [h_enter|spapr_exit]_nested calls for better readability. > > Signed-off-by: Harsh Prateek Bora > Reviewed-by: Fabiano Rosas > --- > hw/ppc/spapr_hcall.c | 18 ++---------------- Could you either convert all callers, or do implementation and conversion as separate patches. Preference for former if you can be bothered. save_user_regs(), restore_user_regs(), gdb read/write register * 2, kvm_arch_get/put_registers, monitor_get_ccr, at a quick glance. > target/ppc/cpu.c | 17 +++++++++++++++++ > target/ppc/cpu.h | 2 ++ > 3 files changed, 21 insertions(+), 16 deletions(-) > > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > index ec4def62f8..124cee5e53 100644 > --- a/hw/ppc/spapr_hcall.c > +++ b/hw/ppc/spapr_hcall.c [snip] > diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c > index 1a97b41c6b..3b444e58b5 100644 > --- a/target/ppc/cpu.c > +++ b/target/ppc/cpu.c > @@ -67,6 +67,23 @@ uint32_t ppc_get_vscr(CPUPPCState *env) > return env->vscr | (sat << VSCR_SAT); > } > =20 > +void ppc_store_cr(CPUPPCState *env, uint64_t cr) Set is normal counterpart to get. Or load and store, but I think set and get is probably better. Good refactoring though, it shouldn't be open-coded everywhere. Thanks, Nick > +{ > + for (int i =3D 7; i >=3D 0; i--) { > + env->crf[i] =3D cr & 15; > + cr >>=3D 4; > + } > +} > + > +uint64_t ppc_get_cr(CPUPPCState *env) > +{ > + uint64_t cr =3D 0; > + for (int i =3D 0; i < 8; i++) { > + cr |=3D (env->crf[i] & 15) << (4 * (7 - i)); > + } > + return cr; > +} > + > /* GDBstub can read and write MSR... */ > void ppc_store_msr(CPUPPCState *env, target_ulong value) > { > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 557d736dab..b4c21459f1 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -2773,6 +2773,8 @@ void dump_mmu(CPUPPCState *env); > void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int le= n); > void ppc_store_vscr(CPUPPCState *env, uint32_t vscr); > uint32_t ppc_get_vscr(CPUPPCState *env); > +void ppc_store_cr(CPUPPCState *env, uint64_t cr); > +uint64_t ppc_get_cr(CPUPPCState *env); > =20 > /***********************************************************************= ******/ > /* Power management enable checks = */ > --=20 > 2.31.1