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[203.219.189.129]) by smtp.gmail.com with ESMTPSA id y15-20020a17090264cf00b001ab01b909c9sm15147839pli.120.2023.05.16.02.42.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 May 2023 02:42:48 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 16 May 2023 19:42:43 +1000 Message-Id: Cc: Subject: Re: [PATCH] target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs From: "Nicholas Piggin" To: "Harsh Prateek Bora" , X-Mailer: aerc 0.14.0 References: <20230515160131.394562-1-npiggin@gmail.com> <4b1147e0-498d-e3ae-d97a-4063055099b1@linux.ibm.com> In-Reply-To: <4b1147e0-498d-e3ae-d97a-4063055099b1@linux.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=npiggin@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue May 16, 2023 at 6:43 PM AEST, Harsh Prateek Bora wrote: > > > On 5/15/23 21:31, Nicholas Piggin wrote: > > QEMU's PVR value for POWER9 DD2.0 has chip type 1, which is the SMT4 > > "small core" type that OpenPOWER processors use. QEMU's PVR for all > > other POWER9/10 have chip type 0, which "enterprise" systems use. > >=20 > > The difference does not really matter to QEMU (because it does not care > > about SMT mode in the target), but for consistency all PVRs should use > > the same chip type. We'll go with the SMT4 OpenPOWER type. > >=20 > > Signed-off-by: Nicholas Piggin > > --- > > This is a replacement for > >=20 > > https://lists.gnu.org/archive/html/qemu-ppc/2022-03/msg00227.html > >=20 > > But the chip type is changed to 1 instead of 0, because that's the > > more familiar SM4 / small core CPU. > >=20 > > Thanks, > > Nick > >=20 > > target/ppc/cpu-models.h | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > >=20 > > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h > > index 1326493a9a..a77e036b3a 100644 > > --- a/target/ppc/cpu-models.h > > +++ b/target/ppc/cpu-models.h > > @@ -348,11 +348,11 @@ enum { > > CPU_POWERPC_POWER8NVL_BASE =3D 0x004C0000, > > CPU_POWERPC_POWER8NVL_v10 =3D 0x004C0100, > > CPU_POWERPC_POWER9_BASE =3D 0x004E0000, > > - CPU_POWERPC_POWER9_DD1 =3D 0x004E0100, > > + CPU_POWERPC_POWER9_DD1 =3D 0x004E1100, > > Could you please point me to the doc location you are referring here? > The P9 UM document that I have access to mentions this bit (0/1) for=20 > 12/24 cores. Not sure if this change is intended here. Yes that's the one, OpenPOWER POWER9 User Manual lists it in PVR. POWER10 is the same. Thanks, Nick