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charset=UTF-8 Date: Fri, 02 Jun 2023 16:56:31 +1000 Message-Id: Subject: Re: [RFC PATCH 4/5] target/ppc: Add msgsnd/p and DPDES SMT support From: "Nicholas Piggin" To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Cc: , "Daniel Henrique Barboza" X-Mailer: aerc 0.14.0 References: <20230531012313.19891-1-npiggin@gmail.com> <20230531012313.19891-5-npiggin@gmail.com> <60f0d393-f0b5-cc06-feff-a8f00e5a32b3@kaod.org> In-Reply-To: <60f0d393-f0b5-cc06-feff-a8f00e5a32b3@kaod.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=npiggin@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu Jun 1, 2023 at 5:13 PM AEST, C=C3=A9dric Le Goater wrote: > On 5/31/23 03:23, Nicholas Piggin wrote: > > Doorbells in SMT need to coordinate msgsnd/msgclr and DPDES access from > > multiple threads that affect the same state. > >=20 > > Signed-off-by: Nicholas Piggin > > --- > > hw/ppc/ppc.c | 6 ++ > > include/hw/ppc/ppc.h | 1 + > > target/ppc/cpu.h | 7 +- > > target/ppc/excp_helper.c | 86 +++++++++++++-----= - > > target/ppc/gdbstub.c | 2 +- > > target/ppc/helper.h | 2 +- > > target/ppc/misc_helper.c | 60 +++++++++++-- > > target/ppc/translate.c | 8 ++ > > .../ppc/translate/processor-ctrl-impl.c.inc | 2 +- > > 9 files changed, 140 insertions(+), 34 deletions(-) > >=20 > > diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c > > index 80b4706db2..e30853413b 100644 > > --- a/hw/ppc/ppc.c > > +++ b/hw/ppc/ppc.c > > @@ -1434,6 +1434,12 @@ int ppc_cpu_pir(PowerPCCPU *cpu) > > return env->spr_cb[SPR_PIR].default_value; > > } > > =20 > > +int ppc_cpu_tir(PowerPCCPU *cpu) > > +{ > > + CPUPPCState *env =3D &cpu->env; > > + return env->spr_cb[SPR_PIR].default_value; > > PIR or TIR ? Good catch, I think I "tidied" that up before sending it :\ > > @@ -3154,22 +3172,42 @@ void helper_book3s_msgclrp(CPUPPCState *env, ta= rget_ulong rb) > > } > > =20 > > /* > > - * sends a message to other threads that are on the same > > + * sends a message to another thread on the same > > * multi-threaded processor > > */ > > void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) > > { > > - int pir =3D env->spr_cb[SPR_PIR].default_value; > > + CPUState *cs =3D env_cpu(env); > > + PowerPCCPU *cpu =3D POWERPC_CPU(cs); > > + CPUState *ccs; > > + uint32_t nr_threads =3D cs->nr_threads; > > + int ttir =3D rb & PPC_BITMASK(57, 63); > > =20 > > helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_= MSGP); > > =20 > > - if (!dbell_type_server(rb)) { > > + if (!dbell_type_server(rb) || ttir >=3D nr_threads) { > > may be log bad ttir values ? even if the insn is a no-op in that case, > telling the user would be good since it should be a guest os issue Yeah. We don't seem to do that on a systematic basis in PPC but we probably should. It's certainly helped me before when I've got something wrong. Good idea. > > @@ -192,14 +192,38 @@ void helper_store_pcr(CPUPPCState *env, target_ul= ong value) > > */ > > target_ulong helper_load_dpdes(CPUPPCState *env) > > { > > + CPUState *cs =3D env_cpu(env); > > + CPUState *ccs; > > + uint32_t nr_threads =3D cs->nr_threads; > > + uint32_t core_id =3D env->spr[SPR_PIR] & ~(nr_threads - 1); > > you could add an helper for the above. Yes. Thanks, Nick