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From: "Nicholas Piggin" <npiggin@gmail.com>
To: "BALATON Zoltan" <balaton@eik.bme.hu>, <qemu-devel@nongnu.org>,
	<qemu-ppc@nongnu.org>
Cc: <clg@kaod.org>, "Greg Kurz" <groug@kaod.org>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>
Subject: Re: [PATCH 08/10] target/ppc: Fix gen_sc to use correct nip
Date: Wed, 14 Jun 2023 13:47:51 +1000	[thread overview]
Message-ID: <CTC2DN50X8A2.2UVS9YQ2HNYJ9@wheely> (raw)
In-Reply-To: <7ae167986e18144bc665bbdd836b49fe723a90a1.1686522199.git.balaton@eik.bme.hu>

On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back but correctly set nip to
> pc_next so we don't have to patch this in the exception handlers.
>
> This changes the nip logged in dump_syscall and dump_hcall debug
> functions but now this matches how nip would be on a real CPU.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>  target/ppc/excp_helper.c | 39 ---------------------------------------
>  target/ppc/translate.c   |  8 +++++---
>  2 files changed, 5 insertions(+), 42 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 885e479301..4f6a6dfb19 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -493,12 +493,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
>          break;
>      case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
>          dump_syscall(env);
> -
> -        /*
> -         * We need to correct the NIP which in this case is supposed
> -         * to point to the next instruction
> -         */
> -        env->nip += 4;
>          break;
>      case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
>          trace_ppc_excp_print("FIT");
> @@ -609,12 +603,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>          break;
>      case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
>          dump_syscall(env);
> -
> -        /*
> -         * We need to correct the NIP which in this case is supposed
> -         * to point to the next instruction
> -         */
> -        env->nip += 4;
>          break;
>      case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
>      case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
> @@ -757,13 +745,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
>          } else {
>              dump_syscall(env);
>          }
> -
> -        /*
> -         * We need to correct the NIP which in this case is supposed
> -         * to point to the next instruction
> -         */
> -        env->nip += 4;
> -
>          /*
>           * The Virtual Open Firmware (VOF) relies on the 'sc 1'
>           * instruction to communicate with QEMU. The pegasos2 machine
> @@ -908,13 +889,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
>          } else {
>              dump_syscall(env);
>          }
> -
> -        /*
> -         * We need to correct the NIP which in this case is supposed
> -         * to point to the next instruction
> -         */
> -        env->nip += 4;
> -
>          /*
>           * The Virtual Open Firmware (VOF) relies on the 'sc 1'
>           * instruction to communicate with QEMU. The pegasos2 machine
> @@ -1073,12 +1047,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
>          break;
>      case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
>          dump_syscall(env);
> -
> -        /*
> -         * We need to correct the NIP which in this case is supposed
> -         * to point to the next instruction
> -         */
> -        env->nip += 4;
>          break;
>      case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
>      case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
> @@ -1320,13 +1288,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>          } else {
>              dump_syscall(env);
>          }
> -
> -        /*
> -         * We need to correct the NIP which in this case is supposed
> -         * to point to the next instruction
> -         */
> -        env->nip += 4;
> -
>          /* "PAPR mode" built-in hypercall emulation */
>          if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
>              PPCVirtualHypervisorClass *vhc =
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index a32a9b8a5f..4260d3d66f 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4419,10 +4419,12 @@ static void gen_hrfid(DisasContext *ctx)
>  #endif
>  static void gen_sc(DisasContext *ctx)
>  {
> -    uint32_t lev;
> +    uint32_t lev = (ctx->opcode >> 5) & 0x7F;
>  
> -    lev = (ctx->opcode >> 5) & 0x7F;
> -    gen_exception_err(ctx, POWERPC_SYSCALL, lev);
> +    gen_update_nip(ctx, ctx->base.pc_next);
> +    gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(POWERPC_SYSCALL),
> +                                   tcg_constant_i32(lev));
> +    ctx->base.is_jmp = DISAS_NORETURN;

Generally for blame and bisect I don't like to mix cleanup with real
change, I guess this is pretty minor though.

Great cleanup though, sc is certainly defined to set SRR0 to the
instruction past the sc unlike other interrupts so it is more natural
and less hacky feeling do it like this.

Could you do scv while you are here? It has the same semantics as
sc.

Thanks,
Nick


  reply	other threads:[~2023-06-14  3:48 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-11 22:42 [PATCH 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
2023-06-11 22:42 ` [PATCH 01/10] target/ppc: Remove some superfluous parentheses BALATON Zoltan
2023-06-14  3:25   ` Nicholas Piggin
2023-06-11 22:42 ` [PATCH 02/10] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup() BALATON Zoltan
2023-06-14  3:26   ` Nicholas Piggin
2023-06-11 22:42 ` [PATCH 03/10] target/ppc: Move common check in exception handlers to a function BALATON Zoltan
2023-06-12  9:28   ` Philippe Mathieu-Daudé
2023-06-12 10:07     ` BALATON Zoltan
2023-06-14  3:35   ` Nicholas Piggin
2023-06-14  6:25     ` Cédric Le Goater
2023-06-15  1:50       ` Nicholas Piggin
2023-06-11 22:42 ` [PATCH 04/10] target/ppc: Use env_cpu for cpu_abort in excp_helper BALATON Zoltan
2023-06-14  3:36   ` Nicholas Piggin
2023-06-14 10:13     ` BALATON Zoltan
2023-06-15  1:01       ` Nicholas Piggin
2023-06-11 22:42 ` [PATCH 05/10] target/ppc: Change parameter of cpu_interrupt_exittb() to an env pointer BALATON Zoltan
2023-06-11 22:42 ` [PATCH 06/10] target/ppc: Readability improvements in exception handlers BALATON Zoltan
2023-06-14  3:42   ` Nicholas Piggin
2023-06-14 10:07     ` BALATON Zoltan
2023-06-15  0:59       ` Nicholas Piggin
2023-06-11 22:42 ` [PATCH 07/10] target/ppd: Remove unused define BALATON Zoltan
2023-06-12  9:29   ` Philippe Mathieu-Daudé
2023-06-14  3:42   ` Nicholas Piggin
2023-06-11 22:42 ` [PATCH 08/10] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2023-06-14  3:47   ` Nicholas Piggin [this message]
2023-06-14 10:05     ` BALATON Zoltan
2023-06-14 21:27     ` BALATON Zoltan
2023-06-15  1:43       ` Nicholas Piggin
2023-06-15 23:02         ` BALATON Zoltan
2023-06-11 22:42 ` [PATCH 09/10] target/ppc: Simplify syscall exception handlers BALATON Zoltan
2023-06-14  4:18   ` Nicholas Piggin
2023-06-14 21:33     ` BALATON Zoltan
2023-06-15  1:47       ` Nicholas Piggin
2023-06-11 22:42 ` [PATCH 10/10] target/ppc: Get CPUState in one step BALATON Zoltan

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