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[220.244.204.78]) by smtp.gmail.com with ESMTPSA id iw15-20020a170903044f00b001aae909cfbbsm6117244plb.119.2023.06.13.22.14.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Jun 2023 22:14:10 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 14 Jun 2023 15:14:05 +1000 Message-Id: Subject: Re: [PATCH 0/4] ppc/pnv: Add chiptod and core timebase state machine models From: "Nicholas Piggin" To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Cc: , "Daniel Henrique Barboza" , "Frederic Barrat" , "Michael Neuling" X-Mailer: aerc 0.14.0 References: <20230603233612.125879-1-npiggin@gmail.com> In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=npiggin@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue Jun 6, 2023 at 11:59 PM AEST, C=C3=A9dric Le Goater wrote: > On 6/4/23 01:36, Nicholas Piggin wrote: > > This adds support for chiptod and core timebase state machine models in > > the powernv POWER9 and POWER10 models. > >=20 > > This does not actually change the time or the value in TB registers > > (because they are alrady synced in QEMU), but it does go through the > > motions. It is enough to be able to run skiboot's chiptod initialisatio= n > > code that synchronises core timebases (after a patch to prevent skiboot > > skipping chiptod for QEMU, posted to skiboot mailing list). > >=20 > > Sorry there was some delay since the last posting. There is a bit more > > interest in this recently but feedback and comments from RFC was not > > forgotten and is much appreciated. > >=20 > > https://lists.gnu.org/archive/html/qemu-ppc/2022-08/msg00324.html > >=20 > > I think I accounted for everything except moving register defines to th= e > > .h file. I'm on the fence about that but if they are only used in the .= c > > file I think it's okay to keep them there for now. I cut out a lot of > > unused ones so it's not so cluttered now. > >=20 > > Lots of other changes and fixes since that RFC. Notably: > > - Register names changed to match the workbook names instead of skiboot= . > > - TFMR moved to timebase_helper.c from misc_helper.c > > - More comprehensive model and error checking, particularly of TFMR. > > - POWER10 with multi-chip support. > > - chiptod and core timebase linked via specific state instead of TFMR. > > > The chiptod units are not exposed to the OS, it is all handled at FW > level AFAIK. Could the OPAL people provide some feedback on the low level > models ? Well, no takers so far. I guess I'm a OPAL people :) I did some of the P10 chiptod addressing in skiboot, at least. This patch does work with the skiboot chiptod driver at least. I would eventually like to add in the ability to actually change the TB with it, and inject errors and generate HMIs because that's an area that seem to be a bit lacking (most of such testing seemed to be done on real hardware using special time facility corruption injection). But yes for now it is a bit difficult to verify it does much useful aside from booting skiboot (+ patch to enable chiptod on QEMU I posted recently). Thanks, Nick