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[14.203.144.223]) by smtp.gmail.com with ESMTPSA id p4-20020a1709026b8400b001b034d2e71csm12000688plk.34.2023.06.14.04.56.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jun 2023 04:56:24 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 14 Jun 2023 21:56:20 +1000 Message-Id: Cc: , "Daniel Henrique Barboza" Subject: Re: [PATCH 2/4] ppc/spapr: Add a nested state struct From: "Nicholas Piggin" To: "Harsh Prateek Bora" , X-Mailer: aerc 0.14.0 References: <20230608091344.88685-1-npiggin@gmail.com> <20230608091344.88685-3-npiggin@gmail.com> In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Jun 9, 2023 at 5:09 PM AEST, Harsh Prateek Bora wrote: > > > On 6/8/23 14:43, Nicholas Piggin wrote: > > Rather than use a copy of CPUPPCState to store the host state while > > the environment has been switched to the L2, use a new struct for > > this purpose. > >=20 > > Have helper functions to save and load this host state. > >=20 > > Signed-off-by: Nicholas Piggin > > --- > > hw/ppc/spapr_hcall.c | 150 ++++++++++++++++++++++++-------= - > > include/hw/ppc/spapr_cpu_core.h | 5 +- > > 2 files changed, 115 insertions(+), 40 deletions(-) > >=20 > > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > > index 0582b524d1..d5b8d54692 100644 > > --- a/hw/ppc/spapr_hcall.c > > +++ b/hw/ppc/spapr_hcall.c > > @@ -1546,6 +1546,112 @@ static target_ulong h_copy_tofrom_guest(PowerPC= CPU *cpu, > > return H_FUNCTION; > > } > > =20 > > +struct nested_ppc_state { > > + uint64_t gpr[32]; > > + uint64_t lr; > > + uint64_t ctr; > > + uint64_t cfar; > > + uint64_t msr; > > + uint64_t nip; > > + uint32_t cr; > > + > > + uint64_t xer; > > + > > + uint64_t lpcr; > > + uint64_t lpidr; > > + uint64_t pidr; > > + uint64_t pcr; > > + uint64_t dpdes; > > + uint64_t hfscr; > > + uint64_t srr0; > > + uint64_t srr1; > > + uint64_t sprg0; > > + uint64_t sprg1; > > + uint64_t sprg2; > > + uint64_t sprg3; > > + uint64_t ppr; > > + > > + int64_t tb_offset; > > +}; > > + > > > > > +static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state= *load) > > +{ > > + CPUState *cs =3D CPU(cpu); > > + CPUPPCState *env =3D &cpu->env; > > + > > + memcpy(env->gpr, load->gpr, sizeof(env->gpr)); > > + > > + env->lr =3D load->lr; > > + env->ctr =3D load->ctr; > > + env->cfar =3D load->cfar; > > + env->msr =3D load->msr; > > + env->nip =3D load->nip; > > + > > + ppc_set_cr(env, load->cr); > > + cpu_write_xer(env, load->xer); > > + > > + env->spr[SPR_LPCR] =3D load->lpcr; > > + env->spr[SPR_LPIDR] =3D load->lpidr; > > + env->spr[SPR_PCR] =3D load->pcr; > > + env->spr[SPR_DPDES] =3D load->dpdes; > > + env->spr[SPR_HFSCR] =3D load->hfscr; > > + env->spr[SPR_SRR0] =3D load->srr0; > > + env->spr[SPR_SRR1] =3D load->srr1; > > + env->spr[SPR_SPRG0] =3D load->sprg0; > > + env->spr[SPR_SPRG1] =3D load->sprg1; > > + env->spr[SPR_SPRG2] =3D load->sprg2; > > + env->spr[SPR_SPRG3] =3D load->sprg3; > > + env->spr[SPR_BOOKS_PID] =3D load->pidr; > > + env->spr[SPR_PPR] =3D load->ppr; > > + > > + env->tb_env->tb_offset =3D load->tb_offset; > > + > > + /* > > + * MSR updated, compute hflags and possible interrupts. > > + */ > > + hreg_compute_hflags(env); > > + ppc_maybe_interrupt(env); > > + > > + /* > > + * Nested HV does not tag TLB entries between L1 and L2, so must > > + * flush on transition. > > + */ > > + tlb_flush(cs); > > + env->reserve_addr =3D -1; /* Reset the reservation */ > > +} > > + > > > > > @@ -1766,34 +1872,8 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp= ) > > address_space_unmap(CPU(cpu)->as, regs, len, len, true); > > =20 > > out_restore_l1: > > - memcpy(env->gpr, spapr_cpu->nested_host_state->gpr, sizeof(env->gp= r)); > > - env->lr =3D spapr_cpu->nested_host_state->lr; > > - env->ctr =3D spapr_cpu->nested_host_state->ctr; > > - memcpy(env->crf, spapr_cpu->nested_host_state->crf, sizeof(env->cr= f)); > > - env->cfar =3D spapr_cpu->nested_host_state->cfar; > > - env->xer =3D spapr_cpu->nested_host_state->xer; > > - env->so =3D spapr_cpu->nested_host_state->so; > > - env->ca =3D spapr_cpu->nested_host_state->ca; > > - env->ov =3D spapr_cpu->nested_host_state->ov; > > - env->ov32 =3D spapr_cpu->nested_host_state->ov32; > > - env->ca32 =3D spapr_cpu->nested_host_state->ca32; > > Above fields so, ca, ov, ov32, ca32 are not taken care in=20 > nested_load_state, ca being introduced in previous patch. They should be, by cpu_write_xer. Thanks, Nick