From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
"Kautuk Consul" <kconsul@linux.vnet.ibm.com>
Subject: Re: [PATCH 0/4] target/ppc: TCG SMT support for spapr
Date: Tue, 20 Jun 2023 20:45:13 +1000 [thread overview]
Message-ID: <CTHF0GSBVRD5.3FZQQ8143ZVWB@wheely> (raw)
In-Reply-To: <2756fa81-9ab8-0b15-a69e-726b47a43d41@kaod.org>
On Tue Jun 20, 2023 at 8:27 PM AEST, Cédric Le Goater wrote:
> On 6/20/23 12:12, Nicholas Piggin wrote:
> > On Wed Jun 7, 2023 at 12:09 AM AEST, Cédric Le Goater wrote:
> >> On 6/5/23 13:23, Nicholas Piggin wrote:
> >>> Previous RFC here
> >>>
> >>> https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00453.html
> >>>
> >>> This series drops patch 1 from the previous, which is more of
> >>> a standalone bugfix.
> >>>
> >>> Also accounted for Cedric's comments, except a nicer way to
> >>> set cpu_index vs PIR/TIR SPRs, which is not quite trivial.
> >>>
> >>> This limits support for SMT to POWER8 and newer. It is also
> >>> incompatible with nested-HV so that is checked for too.
> >>>
> >>> Iterating CPUs to find siblings for now I kept because similar
> >>> loops exist in a few places, and it is not conceptually
> >>> difficult for SMT, just fiddly code to improve. For now it
> >>> should not be much performane concern.
> >>>
> >>> I removed hypervisor msgsnd support from patch 3, which is not
> >>> required for spapr and added significantly to the patch.
> >>>
> >>> For now nobody has objected to the way shared SPR access is
> >>> handled (serialised with TCG atomics support) so we'll keep
> >>> going with it.
> >>
> >> Cc:ing more people for possible feedback.
> >
> > Not much feedback so I'll plan to go with this.
> >
> > A more performant implementation might try to synchronize
> > threads at the register level rather than serialize everything,
> > but SMT shared registers are not too performance critical so
> > this should do for now.
>
> yes. Could you please rebase this series on upstream ?
Oh yeah I should have said, I will rebase and resend.
> It would be good to add tests for SMT. May be we could extend :
>
> tests/avocado/ppc_pseries.py
>
> with a couple of extra QEMU configs adding 'threads=' (if possible) and
> check :
>
> "CPU maps initialized for Y threads per core"
>
> and
>
> "smp: Brought up 1 node, X*Y CPUs"
>
> ?
Yeah that could be a good idea, I'll try it.
Thanks,
Nick
next prev parent reply other threads:[~2023-06-20 10:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 11:23 [PATCH 0/4] target/ppc: TCG SMT support for spapr Nicholas Piggin
2023-06-05 11:23 ` [PATCH 1/4] target/ppc: Add initial flags and helpers for SMT support Nicholas Piggin
2023-06-05 11:23 ` [PATCH 2/4] target/ppc: Add support for SMT CTRL register Nicholas Piggin
2023-06-07 5:31 ` Cédric Le Goater
2023-06-05 11:23 ` [PATCH 3/4] target/ppc: Add msgsndp and DPDES SMT support Nicholas Piggin
2023-06-05 11:23 ` [PATCH 4/4] spapr: Allow up to 8 threads SMT on POWER8 and newer Nicholas Piggin
2023-06-20 9:27 ` Harsh Prateek Bora
2023-06-20 9:41 ` Nicholas Piggin
2023-06-06 14:09 ` [PATCH 0/4] target/ppc: TCG SMT support for spapr Cédric Le Goater
2023-06-20 10:12 ` Nicholas Piggin
2023-06-20 10:27 ` Cédric Le Goater
2023-06-20 10:45 ` Nicholas Piggin [this message]
2023-06-22 7:26 ` Cédric Le Goater
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