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[193.116.203.37]) by smtp.gmail.com with ESMTPSA id d5-20020a170902cec500b001b54d064a4bsm4920415plg.259.2023.06.22.02.54.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jun 2023 02:54:42 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 22 Jun 2023 19:54:35 +1000 Message-Id: Cc: , "Daniel Henrique Barboza" Subject: Re: [PATCH 0/4] ppc/pnv: Add chiptod and core timebase state machine models From: "Nicholas Piggin" To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , X-Mailer: aerc 0.14.0 References: <20230603233612.125879-1-npiggin@gmail.com> <35689504-df1e-0590-b393-a65673562404@kaod.org> In-Reply-To: <35689504-df1e-0590-b393-a65673562404@kaod.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu Jun 22, 2023 at 5:30 PM AEST, C=C3=A9dric Le Goater wrote: > On 6/4/23 01:36, Nicholas Piggin wrote: > > This adds support for chiptod and core timebase state machine models in > > the powernv POWER9 and POWER10 models. > >=20 > > This does not actually change the time or the value in TB registers > > (because they are alrady synced in QEMU), but it does go through the > > motions. It is enough to be able to run skiboot's chiptod initialisatio= n > > code that synchronises core timebases (after a patch to prevent skiboot > > skipping chiptod for QEMU, posted to skiboot mailing list). > >=20 > > Sorry there was some delay since the last posting. There is a bit more > > interest in this recently but feedback and comments from RFC was not > > forgotten and is much appreciated. > >=20 > > https://lists.gnu.org/archive/html/qemu-ppc/2022-08/msg00324.html > >=20 > > I think I accounted for everything except moving register defines to th= e > > .h file. I'm on the fence about that but if they are only used in the .= c > > file I think it's okay to keep them there for now. I cut out a lot of > > unused ones so it's not so cluttered now. > >=20 > > Lots of other changes and fixes since that RFC. Notably: > > - Register names changed to match the workbook names instead of skiboot= . > > - TFMR moved to timebase_helper.c from misc_helper.c > > - More comprehensive model and error checking, particularly of TFMR. > > - POWER10 with multi-chip support. > > - chiptod and core timebase linked via specific state instead of TFMR. > >=20 > > There is still a vast amount that is not modeled, but most of it relate= d > > to error handling, injection, failover, etc that is very complicated an= d > > not required for normal operation. > >=20 > > Thanks, > > Nick > >=20 > > Nicholas Piggin (4): > > pnv/chiptod: Add POWER9/10 chiptod model > > target/ppc: Tidy POWER book4 SPR registration > > target/ppc: add TFMR SPR implementation with read and write helpers > > target/ppc: Implement core timebase state machine and TFMR > > patch 2-4 could be merged in the next PR. Could you please rebase on > ppc-next and resend ? Good idea, I have a couple of other minor register additions that depend on patch 1 too. > Then we still have 2+ weeks to polish pnv/chiptod which would be a > nice addition to QEMU 8.1. Yeah. Been trying to get to it... Hopefully pseries SMT is close now so I will have some more time. Thanks, Nick