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[193.116.198.102]) by smtp.gmail.com with ESMTPSA id o12-20020a170902d4cc00b001b19d14a3d5sm2223044plg.68.2023.06.25.02.20.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 25 Jun 2023 02:20:54 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sun, 25 Jun 2023 19:20:48 +1000 Message-Id: Cc: , "Christophe Leroy" , "BALATON Zoltan" , "Harsh Prateek Bora" , "Daniel Henrique Barboza" , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "David Gibson" , "Greg Kurz" Subject: Re: [PATCH 3/4] target/ppc: Move common check in machne check handlers to a function From: "Nicholas Piggin" To: "Fabiano Rosas" , X-Mailer: aerc 0.15.2 References: <20230623081953.290875-1-npiggin@gmail.com> <20230623081953.290875-4-npiggin@gmail.com> <87edm2s4bh.fsf@suse.de> In-Reply-To: <87edm2s4bh.fsf@suse.de> Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=npiggin@gmail.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Jun 23, 2023 at 11:20 PM AEST, Fabiano Rosas wrote: > Nicholas Piggin writes: > > > From: BALATON Zoltan > > > > All powerpc exception handlers share some code when handling machine > > check exceptions. Move this to a common function. > > > > Maybe Machine Check is simple enough, but this kind of sharing of code > has historically caused pain when people want to change something for > the modern cpus and end up affecting the old cpus by mistake. > > There is also the inverse scenario where someone has access to the old > HW and just want to make an one-off contribution, but the community gets > insecure about it because it could also affect the new cpus. > > Then comes the obvious "solution" which is to bring in an artificial > identifier (excp. model) to be able to have conditional code inside the > common function. And that causes problems because no one really knows > how it maps to actual hardware/ISA. > > No objection, just a little cautionary tale. =3D) Thanks Fabiano, good point. I know you spent a lot of work on untangling this mess. I'll think a bit more about it. Seems we need to at least make a few fixes first before we can turn this on for upstream. Thanks, Nick