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[14.200.238.131]) by smtp.gmail.com with ESMTPSA id jm24-20020a17090304d800b001aaecc15d66sm3956318plb.289.2023.06.26.04.25.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Jun 2023 04:26:00 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 26 Jun 2023 21:25:55 +1000 Message-Id: Cc: , , , "Greg Kurz" , "Daniel Henrique Barboza" Subject: Re: [PATCH v3 09/14] target/ppc: Move patching nip from exception handler to helper_scv From: "Nicholas Piggin" To: "BALATON Zoltan" X-Mailer: aerc 0.15.2 References: In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=npiggin@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue Jun 20, 2023 at 8:47 PM AEST, BALATON Zoltan wrote: > On Tue, 20 Jun 2023, Nicholas Piggin wrote: > > On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote: > >> From: Nicholas Piggin > >> > >> Unlike sc, for scv a facility unavailable interrupt must be generated > >> if FSCR[SCV]=3D0 so we can't raise the exception with nip set to next > >> instruction but we can move advancing nip if the FSCR check passes to > >> helper_scv so the exception handler does not need to change it. > >> > >> [balaton: added commit message] > >> Signed-off-by: BALATON Zoltan > > > > Ah you sent it, fine, thank you. But actually now I look again, > > now we're off by one in the other direction for the dumps. > > This is mentioned in the commit message for the patch changing sc. I thin= k=20 > we should not patch nip in the dump so we actually dump what the CPU=20 > should have and match the ISA docs. > > > So... probably your way is still better because it matches the > > interrupt semantics of the ISA when executing the instruction, > > but it needs this patch: > > OK so then I'm confused why we need nip - 4 in dumps? Sorry I missed your reply here. We want nip - 4 in dumps so the address of the syscall is the sc instruction itself, not the random one after it. Thanks, Nick