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[220.244.154.206]) by smtp.gmail.com with ESMTPSA id q25-20020a62ae19000000b0067a50223e44sm8249401pff.74.2023.07.01.03.22.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Jul 2023 03:22:32 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sat, 01 Jul 2023 20:22:27 +1000 Message-Id: Cc: , Subject: Re: [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom From: "Nicholas Piggin" To: "Joel Stanley" , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= X-Mailer: aerc 0.15.2 References: <20230630035547.80329-1-joel@jms.id.au> <20230630035547.80329-5-joel@jms.id.au> In-Reply-To: <20230630035547.80329-5-joel@jms.id.au> Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Jun 30, 2023 at 1:55 PM AEST, Joel Stanley wrote: > Firmware now warns if booting in LPAR per core mode (PPC bit 62). So > this warning doesn't trigger report the core thread state is 0. > > Signed-off-by: Joel Stanley > --- > hw/ppc/pnv_core.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 7fff2fd9e298..98356d7f6538 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_op= s =3D { > #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d > #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a > =20 > +#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 > + > static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, > unsigned int width) > { > @@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaq= ue, hwaddr addr, > case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: > val =3D 0x0; > break; > + case PNV9_XSCOM_EC_CORE_THREAD_STATE: > + val =3D 0; > + break; > default: > qemu_log_mask(LOG_UNIMP, "Warning: reading reg=3D0x%" HWADDR_PRI= x "\n", > addr); > @@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_op= s =3D { > * POWER10 Quads > */ > =20 > +#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412 > + > static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, > unsigned int width) > { > @@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opa= que, hwaddr addr, > uint64_t val =3D -1; > =20 > switch (offset) { > + case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE: > + val =3D 0; > + break; > default: > qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, > offset); Yeah this is the problem, this is just addressing one core in the quad. AFAIKS P9 may have the same problem though so I don't blame the confusion. The other patches seem good because we'll want a P10 quad too I think. Thanks, Nick