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[193.116.64.199]) by smtp.gmail.com with ESMTPSA id ji2-20020a170903324200b001b89536974bsm2632407plb.202.2023.07.11.19.21.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Jul 2023 19:21:18 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 12 Jul 2023 12:21:13 +1000 Message-Id: Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , , Subject: Re: [PATCH v2] ppc/pnv: Add QME region for P10 From: "Nicholas Piggin" To: "Joel Stanley" X-Mailer: aerc 0.15.2 References: <20230707071213.9924-1-joel@jms.id.au> In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon Jul 10, 2023 at 10:25 AM AEST, Joel Stanley wrote: > On Sat, 8 Jul 2023 at 01:17, Nicholas Piggin wrote: > > > > --- a/include/hw/ppc/pnv_xscom.h > > > +++ b/include/hw/ppc/pnv_xscom.h > > > @@ -127,6 +127,17 @@ struct PnvXScomInterfaceClass { > > > #define PNV10_XSCOM_EC(proc) \ > > > ((0x2 << 16) | ((1 << (3 - (proc))) << 12)) > > > > > > +#define PNV10_XSCOM_QME(chiplet) \ > > > + (PNV10_XSCOM_EQ(chiplet) | (0xE << 16)) > > > + > > > +/* > > > + * Make the region larger by 0x1000 (instead of starting at an offse= t) so the > > > + * modelled addresses start from 0 > > > + */ > > > +#define PNV10_XSCOM_QME_BASE(core) \ > > > + ((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core))) > > > +#define PNV10_XSCOM_QME_SIZE (0x8000 + 0x1000) > > > > I couldn't work out this comment. > > I was trying to describe why we have the + 0x1000. > > Each core sets a bit in the xscom address space, with the first core > setting bit 12, second bit 13, etc. So there's actually no registers > at PNV10_XSCOM_QME_BASE, but so the addressing is easier to follow, I > chose to start the base where we do, and make the region 0x1000 > bigger. > > That was my understanding at least. Ah okay that does make sense. Because you have the core number in the address and core number encoding is one-hot, you don't start at zero or end at 0x4000. It makes sense after you stare at QME model, but maybe could comment the scheme briefly there... and now I think about it, I wonder if QME can actually do broadcast ops to the cores. We don't use that in skiboot but ISTR it could be done, so size might be 0x10000. Thanks, Nick