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[193.116.195.56]) by smtp.gmail.com with ESMTPSA id a17-20020a170902ecd100b001ba066c589dsm2128799plh.137.2023.07.20.19.38.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Jul 2023 19:38:07 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 21 Jul 2023 12:38:01 +1000 Message-Id: Subject: Re: [PATCH v2] target/ppc: Generate storage interrupts for radix RC changes From: "Nicholas Piggin" To: "Shawn Anastasio" , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Cc: , "Greg Kurz" , "David Gibson" , "Daniel Henrique Barboza" , "Timothy Pearson" , "Frederic Barrat" X-Mailer: aerc 0.15.2 References: <20230712161322.2729950-1-sanastasio@raptorengineering.com> <1004ffbe-8855-75d1-45e7-65360bfd1807@raptorengineering.com> In-Reply-To: <1004ffbe-8855-75d1-45e7-65360bfd1807@raptorengineering.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=npiggin@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu Jul 13, 2023 at 3:35 AM AEST, Shawn Anastasio wrote: > On 7/12/23 11:56 AM, C=C3=A9dric Le Goater wrote: > > Hello Shawn, > >=20 > > On 7/12/23 18:13, Shawn Anastasio wrote: > >> Change radix model to always generate a storage interrupt when the R/C > >> bits are not set appropriately in a PTE instead of setting the bits > >> itself. According to the ISA both behaviors are valid, but in practic= e > >> this change more closely matches behavior observed on the POWER9 CPU. > >=20 > > How did you spotted this dark corner case in emulation ? Do you have > > MMU unit tests ? > > I'm currently porting Xen to Power and have been using QEMU's powernv > model extensively for early bring up. I noticed the issue when my radix > implementation worked in QEMU but failed on actual hardware since I > didn't have a proper storage interrupt handler implemented. Cool. This was on my todo list because we rely on it for nested HV KVM too. I actually didn't know about that odd effLIPD=3D0 exception, but it looks right. How did you test that, by running with MSR[HV]=3D0 and LPIDR=3D0 ? For the patch, Reviewed-by: Nicholas Piggin Thanks, Nick