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[61.68.137.140]) by smtp.gmail.com with ESMTPSA id e15-20020aa78c4f000000b00666e883757fsm9723242pfd.123.2023.08.09.04.20.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Aug 2023 04:20:40 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 09 Aug 2023 21:20:36 +1000 Message-Id: Cc: , Subject: Re: [PATCH v2 4/7] tcg/ppc: Use PLD in tcg_out_movi for constant pool From: "Nicholas Piggin" To: "Richard Henderson" , X-Mailer: aerc 0.15.2 References: <20230808030250.50602-1-richard.henderson@linaro.org> <20230808030250.50602-5-richard.henderson@linaro.org> In-Reply-To: <20230808030250.50602-5-richard.henderson@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue Aug 8, 2023 at 1:02 PM AEST, Richard Henderson wrote: > The prefixed instruction has a pc-relative form to use here. I don't understand this code very well but going by existing relocs it looks okay. Reviewed-by: Nicholas Piggin > > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target.c.inc | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index 61ae9d8ab7..b3b2e9874d 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -101,6 +101,10 @@ > #define ALL_GENERAL_REGS 0xffffffffu > #define ALL_VECTOR_REGS 0xffffffff00000000ull > =20 > +#ifndef R_PPC64_PCREL34 > +#define R_PPC64_PCREL34 132 > +#endif > + > #define have_isel (cpuinfo & CPUINFO_ISEL) > =20 > #ifndef CONFIG_SOFTMMU > @@ -260,6 +264,19 @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const = tcg_insn_unit *target) > return false; > } > =20 > +static bool reloc_pc34(tcg_insn_unit *src_rw, const tcg_insn_unit *targe= t) > +{ > + const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); > + ptrdiff_t disp =3D tcg_ptr_byte_diff(target, src_rx); > + > + if (disp =3D=3D sextract64(disp, 0, 34)) { > + src_rw[0] =3D (src_rw[0] & ~0x3ffff) | ((disp >> 16) & 0x3ffff); > + src_rw[1] =3D (src_rw[1] & ~0xffff) | (disp & 0xffff); > + return true; > + } > + return false; > +} > + > /* test if a constant matches the constraint */ > static bool tcg_target_const_match(int64_t val, TCGType type, int ct) > { > @@ -684,6 +701,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, > return reloc_pc14(code_ptr, target); > case R_PPC_REL24: > return reloc_pc24(code_ptr, target); > + case R_PPC64_PCREL34: > + return reloc_pc34(code_ptr, target); > case R_PPC_ADDR16: > /* > * We are (slightly) abusing this relocation type. In particula= r, > @@ -1111,6 +1130,11 @@ static void tcg_out_movi_int(TCGContext *s, TCGTyp= e type, TCGReg ret, > } > =20 > /* Use the constant pool, if possible. */ > + if (have_isa_3_10) { > + tcg_out_8ls_d(s, PLD, ret, 0, 0, 1); > + new_pool_label(s, arg, R_PPC64_PCREL34, s->code_ptr - 2, 0); > + return; > + } > if (!in_prologue && USE_REG_TB) { > new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, > tcg_tbrel_diff(s, NULL));