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[60.240.124.93]) by smtp.gmail.com with ESMTPSA id t11-20020a170902bc4b00b001c72d5e16acsm69441plz.57.2023.11.22.17.34.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Nov 2023 17:34:07 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 23 Nov 2023 11:34:02 +1000 Message-Id: Cc: , , , , , Subject: Re: [PATCH] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U From: "Nicholas Piggin" To: "Saif Abrar" , X-Mailer: aerc 0.15.2 References: <20230918092616.15398-1-saif.abrar@linux.vnet.ibm.com> In-Reply-To: <20230918092616.15398-1-saif.abrar@linux.vnet.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=npiggin@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon Sep 18, 2023 at 7:26 PM AEST, Saif Abrar wrote: > SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState. > Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[]= array. > Update gdb_get_spr_reg() method to handle these SPR's specifically. > > Signed-off-by: Saif Abrar Thanks for this, I have been annoyed by missing those regs when using gdb at times :) > --- > target/ppc/gdbstub.c | 40 ++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 38 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c > index 2ad11510bf..eb086c0168 100644 > --- a/target/ppc/gdbstub.c > +++ b/target/ppc/gdbstub.c > @@ -412,7 +412,32 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteAr= ray *buf, int n) > } > =20 > len =3D TARGET_LONG_SIZE; > - gdb_get_regl(buf, env->spr[reg]); > + > + /* Handle those SPRs that are not part of the env->spr[] array */ > + target_ulong val; Could you move this to the of the block with other declarations? > + switch (reg) { > +#if defined(TARGET_PPC64) > + case SPR_CFAR: > + val =3D env->cfar; > + break; > +#endif > + case SPR_HDEC: > + val =3D cpu_ppc_load_hdecr(env); > + break; > + case SPR_TBL: > + val =3D cpu_ppc_load_tbl(env); > + break; > + case SPR_TBU: > + val =3D cpu_ppc_load_tbu(env); > + break; > + case SPR_DECR: > + val =3D cpu_ppc_load_decr(env); > + break; > + default: > + val =3D env->spr[reg]; > + } > + gdb_get_regl(buf, val); > + > ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); > return len; > } > @@ -429,7 +454,18 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t= *mem_buf, int n) > =20 > len =3D TARGET_LONG_SIZE; > ppc_maybe_bswap_register(env, mem_buf, len); > - env->spr[reg] =3D ldn_p(mem_buf, len); > + > + /* Handle those SPRs that are not part of the env->spr[] array */ > + target_ulong val =3D ldn_p(mem_buf, len); > + switch (reg) { > +#if defined(TARGET_PPC64) > + case SPR_CFAR: > + env->cfar =3D val; > + break; > +#endif I suppose we could store some time regs here too. (h)decr I have found useful to change at times to interrupts when debugging Linux timer code. TB could be similar. We have a bit of weirdness with our timebase registers though, I'm going to send out some patches for them. Maybe hold off changing this until we agree on those. I'll take this for next release, sorry didn't get to it earlier. Thanks, Nick > + default: > + env->spr[reg] =3D val; > + } > =20 > return len; > }