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[121.44.66.27]) by smtp.gmail.com with ESMTPSA id c4-20020aa781c4000000b006cb955dc54csm2696183pfn.58.2023.11.24.03.28.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Nov 2023 03:28:24 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 24 Nov 2023 21:28:17 +1000 Message-Id: Cc: , , , , , Subject: Re: [PATCH v5 3/3] hw/ppc: Nest1 chiplet wiring From: "Nicholas Piggin" To: "Chalapathi V" , X-Mailer: aerc 0.15.2 References: <20231124101534.19454-1-chalapathi.v@linux.ibm.com> <20231124101534.19454-4-chalapathi.v@linux.ibm.com> In-Reply-To: <20231124101534.19454-4-chalapathi.v@linux.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote: > This part of the patchset connects the nest1 chiplet model to p10 chip. Seems fine to me. Should it just be squashed into patch 2? Thanks, Nick > > Signed-off-by: Chalapathi V > --- > include/hw/ppc/pnv_chip.h | 2 ++ > hw/ppc/pnv.c | 14 ++++++++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h > index 0ab5c42308..59a3158a6b 100644 > --- a/include/hw/ppc/pnv_chip.h > +++ b/include/hw/ppc/pnv_chip.h > @@ -4,6 +4,7 @@ > #include "hw/pci-host/pnv_phb4.h" > #include "hw/ppc/pnv_core.h" > #include "hw/ppc/pnv_homer.h" > +#include "hw/ppc/pnv_nest_chiplet.h" > #include "hw/ppc/pnv_lpc.h" > #include "hw/ppc/pnv_occ.h" > #include "hw/ppc/pnv_psi.h" > @@ -113,6 +114,7 @@ struct Pnv10Chip { > PnvOCC occ; > PnvSBE sbe; > PnvHomer homer; > + PnvNest1 nest1; > =20 > uint32_t nr_quads; > PnvQuad *quads; > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 0297871bdd..ba3dfab557 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1680,6 +1680,7 @@ static void pnv_chip_power10_instance_init(Object *= obj) > object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); > object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); > object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOM= ER); > + object_initialize_child(obj, "nest1", &chip10->nest1, TYPE_PNV_NEST1= ); > =20 > chip->num_pecs =3D pcc->num_pecs; > =20 > @@ -1849,6 +1850,19 @@ static void pnv_chip_power10_realize(DeviceState *= dev, Error **errp) > memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(ch= ip), > &chip10->homer.regs); > =20 > + /* nest1 chiplet */ > + if (!qdev_realize(DEVICE(&chip10->nest1), NULL, errp)) { > + return; > + } > + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE, > + &chip10->nest1.perv.xscom_perv_ctrl_regs); > + > + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_PB_SCOM_EQ_BASE, > + &chip10->nest1.xscom_pb_eq_regs); > + > + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_PB_SCOM_ES_BASE, > + &chip10->nest1.xscom_pb_es_regs); > + > /* PHBs */ > pnv_chip_power10_phb_realize(chip, &local_err); > if (local_err) {