From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Harsh Prateek Bora" <harshpb@linux.ibm.com>, <qemu-ppc@nongnu.org>
Cc: <qemu-devel@nongnu.org>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"David Gibson" <david@gibson.dropbear.id.au>
Subject: Re: [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry
Date: Tue, 12 Mar 2024 20:34:15 +1000 [thread overview]
Message-ID: <CZRPCZAA1IT6.1ACEYYVZ27C5D@wheely> (raw)
In-Reply-To: <eb0f5c3b-92ee-4c89-82a4-fcdd9db068b7@linux.ibm.com>
On Tue Mar 12, 2024 at 8:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>
> It would be good to mention PAPR section numbers suggesting the same.
I'll see if I can find it and put it in a comment.
Thanks,
Nick
> Anyways,
>
> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
>
> > ---
> > hw/ppc/spapr_cpu_core.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> > index 50523ead25..f3b01b0801 100644
> > --- a/hw/ppc/spapr_cpu_core.c
> > +++ b/hw/ppc/spapr_cpu_core.c
> > @@ -42,6 +42,8 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
> > * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
> > */
> > env->msr &= ~(1ULL << MSR_SF);
> > + env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
> > +
> > env->spr[SPR_HIOR] = 0;
> >
> > lpcr = env->spr[SPR_LPCR];
next prev parent reply other threads:[~2024-03-12 10:34 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-11 18:51 [PATCH 00/13] misc ppc patches Nicholas Piggin
2024-03-11 18:51 ` [PATCH 01/13] ppc: Drop support for POWER9 and POWER10 DD1 chips Nicholas Piggin
2024-03-12 4:50 ` Harsh Prateek Bora
2024-03-12 4:55 ` Harsh Prateek Bora
2024-03-12 8:59 ` Nicholas Piggin
2024-03-12 9:06 ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 02/13] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
2024-03-12 8:10 ` Harsh Prateek Bora
2024-03-12 8:55 ` Nicholas Piggin
2024-03-11 18:51 ` [PATCH 03/13] ppc/spapr|pnv: Remove SAO from pa-features Nicholas Piggin
2024-03-12 8:40 ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 04/13] ppc/spapr: Remove copy-paste " Nicholas Piggin
2024-03-12 8:49 ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 05/13] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
2024-03-12 9:13 ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 06/13] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
2024-03-11 20:05 ` Philippe Mathieu-Daudé
2024-03-11 21:07 ` BALATON Zoltan
2024-03-12 4:50 ` Nicholas Piggin
2024-03-12 9:59 ` BALATON Zoltan
2024-03-12 10:33 ` Nicholas Piggin
2024-03-12 4:45 ` Nicholas Piggin
2024-03-12 9:34 ` Harsh Prateek Bora
2024-03-12 10:34 ` Nicholas Piggin
2024-03-11 18:51 ` [PATCH 07/13] ppc/pnv: Permit ibm, pa-features set per machine variant Nicholas Piggin
2024-03-12 8:02 ` [PATCH 07/13] ppc/pnv: Permit ibm,pa-features " Cédric Le Goater
2024-03-11 18:51 ` [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
2024-03-12 8:06 ` Cédric Le Goater
2024-03-12 8:54 ` Nicholas Piggin
2024-03-12 9:14 ` Cédric Le Goater
2024-03-11 18:51 ` [PATCH 09/13] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
2024-03-12 10:27 ` Harsh Prateek Bora
2024-03-12 10:33 ` Nicholas Piggin
2024-03-11 18:51 ` [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
2024-03-12 10:03 ` Harsh Prateek Bora
2024-03-12 10:34 ` Nicholas Piggin [this message]
2024-03-11 18:51 ` [PATCH 11/13] target/ppc: Make checkstop actually stop the system Nicholas Piggin
2024-03-11 18:51 ` [PATCH 12/13] target/ppc: improve checkstop logging Nicholas Piggin
2024-03-11 18:51 ` [PATCH 13/13] target/ppc: Implement attn instruction on BookS 64-bit processors Nicholas Piggin
2024-03-11 20:06 ` [PATCH 00/13] misc ppc patches Philippe Mathieu-Daudé
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