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Tue, 12 Mar 2024 04:37:33 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 12 Mar 2024 21:37:27 +1000 Message-Id: Cc: , , , , , , Subject: Re: [PATCH v5 09/14] spapr: nested: Extend nested_ppc_state for nested PAPR API From: "Nicholas Piggin" To: "Harsh Prateek Bora" , X-Mailer: aerc 0.15.2 References: <20240308111940.1617660-1-harshpb@linux.ibm.com> <20240308111940.1617660-10-harshpb@linux.ibm.com> In-Reply-To: <20240308111940.1617660-10-harshpb@linux.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=npiggin@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote: > Currently, nested_ppc_state stores a certain set of registers and works > with nested_[load|save]_state() for state transfer as reqd for nested-hv = API. > Extending these with additional registers state as reqd for nested PAPR A= PI. > > Signed-off-by: Harsh Prateek Bora > Suggested-by: Nicholas Piggin I still have concerns with exactly how registers are saved and restored, but it's not necessarily a new problem with v2, and not so much fundamental design flow more of verifying details so I'm inclined to take this for now. Acked-by: Nicholas Piggin > --- > include/hw/ppc/spapr_nested.h | 50 ++++++++++++++++ > target/ppc/cpu.h | 2 + > hw/ppc/spapr_nested.c | 106 ++++++++++++++++++++++++++++++++++ > 3 files changed, 158 insertions(+) > > diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.= h > index 2ac3076fac..d232014ccb 100644 > --- a/include/hw/ppc/spapr_nested.h > +++ b/include/hw/ppc/spapr_nested.h > @@ -7,6 +7,7 @@ typedef struct SpaprMachineStateNested { > uint64_t ptcr; > uint8_t api; > #define NESTED_API_KVM_HV 1 > +#define NESTED_API_PAPR 2 > bool capabilities_set; > uint32_t pvr_base; > GHashTable *guests; > @@ -121,6 +122,55 @@ struct nested_ppc_state { > uint64_t ppr; > =20 > int64_t tb_offset; > + /* Nested PAPR API */ > + uint64_t amor; > + uint64_t dawr0; > + uint64_t dawrx0; > + uint64_t ciabr; > + uint64_t purr; > + uint64_t spurr; > + uint64_t ic; > + uint64_t vtb; > + uint64_t hdar; > + uint64_t hdsisr; > + uint64_t heir; > + uint64_t asdr; > + uint64_t dawr1; > + uint64_t dawrx1; > + uint64_t dexcr; > + uint64_t hdexcr; > + uint64_t hashkeyr; > + uint64_t hashpkeyr; > + ppc_vsr_t vsr[64] QEMU_ALIGNED(16); > + uint64_t ebbhr; > + uint64_t tar; > + uint64_t ebbrr; > + uint64_t bescr; > + uint64_t iamr; > + uint64_t amr; > + uint64_t uamor; > + uint64_t dscr; > + uint64_t fscr; > + uint64_t pspb; > + uint64_t ctrl; > + uint64_t vrsave; > + uint64_t dar; > + uint64_t dsisr; > + uint64_t pmc1; > + uint64_t pmc2; > + uint64_t pmc3; > + uint64_t pmc4; > + uint64_t pmc5; > + uint64_t pmc6; > + uint64_t mmcr0; > + uint64_t mmcr1; > + uint64_t mmcr2; > + uint64_t mmcra; > + uint64_t sdar; > + uint64_t siar; > + uint64_t sier; > + uint32_t vscr; > + uint64_t fpscr; > }; > =20 > typedef struct SpaprMachineStateNestedGuestVcpu { > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 0133da4e07..4cffd46c79 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1755,9 +1755,11 @@ void ppc_compat_add_property(Object *obj, const ch= ar *name, > #define SPR_PSPB (0x09F) > #define SPR_DPDES (0x0B0) > #define SPR_DAWR0 (0x0B4) > +#define SPR_DAWR1 (0x0B5) > #define SPR_RPR (0x0BA) > #define SPR_CIABR (0x0BB) > #define SPR_DAWRX0 (0x0BC) > +#define SPR_DAWRX1 (0x0BD) > #define SPR_HFSCR (0x0BE) > #define SPR_VRSAVE (0x100) > #define SPR_USPRG0 (0x100) > diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c > index 4c0e2e91e1..09ebf42a57 100644 > --- a/hw/ppc/spapr_nested.c > +++ b/hw/ppc/spapr_nested.c > @@ -108,6 +108,7 @@ static target_ulong h_copy_tofrom_guest(PowerPCCPU *c= pu, > static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU = *cpu) > { > CPUPPCState *env =3D &cpu->env; > + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); > =20 > memcpy(save->gpr, env->gpr, sizeof(save->gpr)); > =20 > @@ -134,6 +135,58 @@ static void nested_save_state(struct nested_ppc_stat= e *save, PowerPCCPU *cpu) > save->pidr =3D env->spr[SPR_BOOKS_PID]; > save->ppr =3D env->spr[SPR_PPR]; > =20 > + if (spapr_nested_api(spapr) =3D=3D NESTED_API_PAPR) { > + save->pvr =3D env->spr[SPR_PVR]; > + save->amor =3D env->spr[SPR_AMOR]; > + save->dawr0 =3D env->spr[SPR_DAWR0]; > + save->dawrx0 =3D env->spr[SPR_DAWRX0]; > + save->ciabr =3D env->spr[SPR_CIABR]; > + save->purr =3D env->spr[SPR_PURR]; > + save->spurr =3D env->spr[SPR_SPURR]; > + save->ic =3D env->spr[SPR_IC]; > + save->vtb =3D env->spr[SPR_VTB]; > + save->hdar =3D env->spr[SPR_HDAR]; > + save->hdsisr =3D env->spr[SPR_HDSISR]; > + save->heir =3D env->spr[SPR_HEIR]; > + save->asdr =3D env->spr[SPR_ASDR]; > + save->dawr1 =3D env->spr[SPR_DAWR1]; > + save->dawrx1 =3D env->spr[SPR_DAWRX1]; > + save->dexcr =3D env->spr[SPR_DEXCR]; > + save->hdexcr =3D env->spr[SPR_HDEXCR]; > + save->hashkeyr =3D env->spr[SPR_HASHKEYR]; > + save->hashpkeyr =3D env->spr[SPR_HASHPKEYR]; > + memcpy(save->vsr, env->vsr, sizeof(save->vsr)); > + save->ebbhr =3D env->spr[SPR_EBBHR]; > + save->tar =3D env->spr[SPR_TAR]; > + save->ebbrr =3D env->spr[SPR_EBBRR]; > + save->bescr =3D env->spr[SPR_BESCR]; > + save->iamr =3D env->spr[SPR_IAMR]; > + save->amr =3D env->spr[SPR_AMR]; > + save->uamor =3D env->spr[SPR_UAMOR]; > + save->dscr =3D env->spr[SPR_DSCR]; > + save->fscr =3D env->spr[SPR_FSCR]; > + save->pspb =3D env->spr[SPR_PSPB]; > + save->ctrl =3D env->spr[SPR_CTRL]; > + save->vrsave =3D env->spr[SPR_VRSAVE]; > + save->dar =3D env->spr[SPR_DAR]; > + save->dsisr =3D env->spr[SPR_DSISR]; > + save->pmc1 =3D env->spr[SPR_POWER_PMC1]; > + save->pmc2 =3D env->spr[SPR_POWER_PMC2]; > + save->pmc3 =3D env->spr[SPR_POWER_PMC3]; > + save->pmc4 =3D env->spr[SPR_POWER_PMC4]; > + save->pmc5 =3D env->spr[SPR_POWER_PMC5]; > + save->pmc6 =3D env->spr[SPR_POWER_PMC6]; > + save->mmcr0 =3D env->spr[SPR_POWER_MMCR0]; > + save->mmcr1 =3D env->spr[SPR_POWER_MMCR1]; > + save->mmcr2 =3D env->spr[SPR_POWER_MMCR2]; > + save->mmcra =3D env->spr[SPR_POWER_MMCRA]; > + save->sdar =3D env->spr[SPR_POWER_SDAR]; > + save->siar =3D env->spr[SPR_POWER_SIAR]; > + save->sier =3D env->spr[SPR_POWER_SIER]; > + save->vscr =3D ppc_get_vscr(env); > + save->fpscr =3D env->fpscr; > + } > + > save->tb_offset =3D env->tb_env->tb_offset; > } > =20 > @@ -141,6 +194,7 @@ static void nested_load_state(PowerPCCPU *cpu, struct= nested_ppc_state *load) > { > CPUState *cs =3D CPU(cpu); > CPUPPCState *env =3D &cpu->env; > + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); > =20 > memcpy(env->gpr, load->gpr, sizeof(env->gpr)); > =20 > @@ -167,6 +221,58 @@ static void nested_load_state(PowerPCCPU *cpu, struc= t nested_ppc_state *load) > env->spr[SPR_BOOKS_PID] =3D load->pidr; > env->spr[SPR_PPR] =3D load->ppr; > =20 > + if (spapr_nested_api(spapr) =3D=3D NESTED_API_PAPR) { > + env->spr[SPR_PVR] =3D load->pvr; > + env->spr[SPR_AMOR] =3D load->amor; > + env->spr[SPR_DAWR0] =3D load->dawr0; > + env->spr[SPR_DAWRX0] =3D load->dawrx0; > + env->spr[SPR_CIABR] =3D load->ciabr; > + env->spr[SPR_PURR] =3D load->purr; > + env->spr[SPR_SPURR] =3D load->purr; > + env->spr[SPR_IC] =3D load->ic; > + env->spr[SPR_VTB] =3D load->vtb; > + env->spr[SPR_HDAR] =3D load->hdar; > + env->spr[SPR_HDSISR] =3D load->hdsisr; > + env->spr[SPR_HEIR] =3D load->heir; > + env->spr[SPR_ASDR] =3D load->asdr; > + env->spr[SPR_DAWR1] =3D load->dawr1; > + env->spr[SPR_DAWRX1] =3D load->dawrx1; > + env->spr[SPR_DEXCR] =3D load->dexcr; > + env->spr[SPR_HDEXCR] =3D load->hdexcr; > + env->spr[SPR_HASHKEYR] =3D load->hashkeyr; > + env->spr[SPR_HASHPKEYR] =3D load->hashpkeyr; > + memcpy(env->vsr, load->vsr, sizeof(env->vsr)); > + env->spr[SPR_EBBHR] =3D load->ebbhr; > + env->spr[SPR_TAR] =3D load->tar; > + env->spr[SPR_EBBRR] =3D load->ebbrr; > + env->spr[SPR_BESCR] =3D load->bescr; > + env->spr[SPR_IAMR] =3D load->iamr; > + env->spr[SPR_AMR] =3D load->amr; > + env->spr[SPR_UAMOR] =3D load->uamor; > + env->spr[SPR_DSCR] =3D load->dscr; > + env->spr[SPR_FSCR] =3D load->fscr; > + env->spr[SPR_PSPB] =3D load->pspb; > + env->spr[SPR_CTRL] =3D load->ctrl; > + env->spr[SPR_VRSAVE] =3D load->vrsave; > + env->spr[SPR_DAR] =3D load->dar; > + env->spr[SPR_DSISR] =3D load->dsisr; > + env->spr[SPR_POWER_PMC1] =3D load->pmc1; > + env->spr[SPR_POWER_PMC2] =3D load->pmc2; > + env->spr[SPR_POWER_PMC3] =3D load->pmc3; > + env->spr[SPR_POWER_PMC4] =3D load->pmc4; > + env->spr[SPR_POWER_PMC5] =3D load->pmc5; > + env->spr[SPR_POWER_PMC6] =3D load->pmc6; > + env->spr[SPR_POWER_MMCR0] =3D load->mmcr0; > + env->spr[SPR_POWER_MMCR1] =3D load->mmcr1; > + env->spr[SPR_POWER_MMCR2] =3D load->mmcr2; > + env->spr[SPR_POWER_MMCRA] =3D load->mmcra; > + env->spr[SPR_POWER_SDAR] =3D load->sdar; > + env->spr[SPR_POWER_SIAR] =3D load->siar; > + env->spr[SPR_POWER_SIER] =3D load->sier; > + ppc_store_vscr(env, load->vscr); > + ppc_store_fpscr(env, load->fpscr); > + } > + > env->tb_env->tb_offset =3D load->tb_offset; > =20 > /*