* [PATCH v7 00/10] Misc clean ups to target/ppc exception handling
@ 2024-02-27 15:08 BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 01/10] target/ppc: Use env_cpu for cpu_abort in excp_helper BALATON Zoltan
` (9 more replies)
0 siblings, 10 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
These are some small clean ups for target/ppc/excp_helper.c trying to
make this code a bit simpler. No functional change is intended. This
series was submitted before but only partially merged due to freeze
and conflicting series os thia was postponed then to avoid conflicts.
v7:
- New patch adding gen_exception_err_nip() as suggested by Nick
- Remove unneeded else branch after return
v6:
- rebase on master
- added R-b tags and changes from Harsh
v5:
- rebase on master
- keep logging nip pointing to the sc instruction
- add another patch
v4: Rebased on master dropping what was merged
BALATON Zoltan (10):
target/ppc: Use env_cpu for cpu_abort in excp_helper
target/ppc: Readability improvements in exception handlers
target/ppc: Add gen_exception_err_nip() function
target/ppc: Fix gen_sc to use correct nip
target/ppc: Move patching nip from exception handler to helper_scv
target/ppc: Simplify syscall exception handlers
target/ppc: Clean up ifdefs in excp_helper.c, part 1
target/ppc: Clean up ifdefs in excp_helper.c, part 2
target/ppc: Clean up ifdefs in excp_helper.c, part 3
target/ppc: Remove interrupt handler wrapper functions
target/ppc/cpu.h | 1 +
target/ppc/excp_helper.c | 485 ++++++++++++---------------------------
target/ppc/translate.c | 40 ++--
3 files changed, 176 insertions(+), 350 deletions(-)
--
2.30.9
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v7 01/10] target/ppc: Use env_cpu for cpu_abort in excp_helper
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers BALATON Zoltan
` (8 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
Use the env_cpu function to get the CPUState for cpu_abort. These are
only needed in case of fatal errors so this allows to avoid casting
and storing CPUState in a local variable wnen not needed.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/excp_helper.c | 118 +++++++++++++++++++++------------------
1 file changed, 63 insertions(+), 55 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 98952de267..56a5fe7f3b 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -445,7 +445,6 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env)
static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -473,8 +472,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -523,7 +522,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
env->spr[SPR_40x_ESR] = ESR_PTR;
break;
default:
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -550,11 +549,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
trace_ppc_excp_print("PIT");
break;
case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -569,7 +569,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
@@ -592,8 +591,8 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -653,7 +652,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -675,8 +674,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset exception "
+ "%d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
@@ -703,11 +703,12 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -730,7 +731,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
@@ -753,8 +753,8 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -812,7 +812,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -854,8 +854,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset exception "
+ "%d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
@@ -875,11 +876,12 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -902,7 +904,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
@@ -925,8 +926,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -984,7 +985,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1026,7 +1027,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
break;
@@ -1039,11 +1041,12 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -1066,7 +1069,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -1103,8 +1105,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -1135,6 +1137,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
if (env->mpic_proxy) {
+ CPUState *cs = env_cpu(env);
/* IACK the IRQ on delivery */
env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
}
@@ -1173,7 +1176,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1214,7 +1217,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
/* DBSR already modified by caller */
} else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ cpu_abort(env_cpu(env),
+ "Debug exception triggered on unsupported model\n");
}
break;
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
@@ -1228,17 +1232,19 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -1376,7 +1382,6 @@ static bool is_prefix_insn_excp(PowerPCCPU *cpu, int excp)
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1, lev = -1;
@@ -1415,8 +1420,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -1512,7 +1517,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1578,7 +1583,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
} else {
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
}
@@ -1650,11 +1656,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_VPUA: /* Vector assist exception */
case POWERPC_EXCP_MAINT: /* Maintenance exception */
case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -1687,8 +1694,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
} else {
/* Sanity check */
if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
+ cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR) %d "
+ "with no HV support\n", excp);
}
/* This can update new_msr and vector if AIL applies */
@@ -1706,11 +1713,11 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
static void powerpc_excp(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
}
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
@@ -2244,7 +2251,6 @@ void ppc_maybe_interrupt(CPUPPCState *env)
static void p7_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_MCK: /* Machine check exception */
@@ -2288,14 +2294,14 @@ static void p7_deliver_interrupt(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
static void p8_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_MCK: /* Machine check exception */
@@ -2359,7 +2365,8 @@ static void p8_deliver_interrupt(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
@@ -2438,7 +2445,8 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
#endif
@@ -2446,7 +2454,6 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_RESET: /* External reset */
@@ -2543,7 +2550,8 @@ static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 01/10] target/ppc: Use env_cpu for cpu_abort in excp_helper BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-02-27 15:32 ` Peter Maydell
2024-02-27 15:08 ` [PATCH v7 03/10] target/ppc: Add gen_exception_err_nip() function BALATON Zoltan
` (7 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract when reading the code.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 1 +
target/ppc/excp_helper.c | 179 +++++++--------------------------------
2 files changed, 33 insertions(+), 147 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ec14574d14..03c7a94a2a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2951,6 +2951,7 @@ static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
}
#if !defined(CONFIG_USER_ONLY)
+/* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 56a5fe7f3b..fba6e03d18 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -403,9 +403,8 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector,
* We don't use hreg_store_msr here as already have treated any
* special case that could occur. Just store MSR and update hflags
*
- * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
- * will prevent setting of the HV bit which some exceptions might need
- * to do.
+ * Note: We *MUST* not use hreg_store_msr() as-is anyway because it will
+ * prevent setting of the HV bit which some exceptions might need to do.
*/
env->nip = vector;
env->msr = msr;
@@ -447,25 +446,15 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden.
- */
+ /* new interrupt handler msr preserves ME unless explicitly overriden */
new_msr = env->msr & (((target_ulong)1 << MSR_ME));
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -475,7 +464,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -487,7 +475,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
srr0 = SPR_40x_SRR2;
srr1 = SPR_40x_SRR3;
break;
@@ -558,12 +545,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
break;
}
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overriden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -594,7 +571,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -604,7 +580,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -632,11 +607,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -712,20 +685,11 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -737,16 +701,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overriden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -756,7 +714,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -764,7 +721,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -792,11 +748,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -865,12 +819,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
ppc_excp_debug_sw_tlb(env, excp);
-
msr |= env->crf[0] << 28;
msr |= env->error_code; /* key, D/I, S/L bits */
/* Set way using a LRU mechanism */
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
-
break;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
@@ -885,20 +837,11 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -910,16 +853,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overriden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -929,7 +866,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -937,7 +873,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -965,11 +900,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -1050,20 +983,11 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -1071,24 +995,18 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
-
- msr = env->msr;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
/*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
+ * Book E does not play games with certain bits of xSRR1 being MSR save
+ * bits and others being error status. xSRR1 is the old MSR, period.
*/
- new_msr = env->msr & ((target_ulong)1 << MSR_ME);
+ msr = env->msr;
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
+ /* new interrupt handler msr preserves ME unless explicitly overriden */
+ new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -1108,7 +1026,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -1152,11 +1069,9 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
env->spr[SPR_BOOKE_ESR] = ESR_FP;
@@ -1257,12 +1172,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
}
#endif
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -1384,21 +1295,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1, lev = -1;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
/*
- * new interrupt handler msr preserves existing HV and ME unless
- * explicitly overridden
+ * new interrupt handler msr preserves HV and ME unless explicitly
+ * overriden
*/
new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
/*
* check for special resume at 0x100 from doze/nap/sleep/winkle on
* P7/P8/P9
@@ -1423,7 +1330,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
if (is_prefix_insn_excp(cpu, excp)) {
@@ -1440,7 +1346,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
*/
new_msr |= (target_ulong)MSR_HVB;
}
-
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -1458,23 +1363,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
bool lpes0;
- /*
- * LPES0 is only taken into consideration if we support HV
- * mode for this CPU.
- */
+ /* LPES0 is only taken into consideration if we support HV mode */
if (!env->has_hv_mode) {
break;
}
-
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
-
if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
}
-
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
@@ -1497,11 +1396,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -1665,21 +1562,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
new_msr |= (target_ulong)1 << MSR_SF;
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
}
@@ -1688,19 +1577,15 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
/* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */
vhc->deliver_hv_excp(cpu, excp);
-
powerpc_reset_excp_state(cpu);
-
} else {
/* Sanity check */
if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR) %d "
"with no HV support\n", excp);
}
-
/* This can update new_msr and vector if AIL applies */
ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
}
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 03/10] target/ppc: Add gen_exception_err_nip() function
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 01/10] target/ppc: Use env_cpu for cpu_abort in excp_helper BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-03-12 12:29 ` Nicholas Piggin
2024-02-27 15:08 ` [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
` (6 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
Add gen_exception_err_nip() that does the same as gen_exception_err()
but takes the nip as a parameter to allow specifying it instead of
using the current instruction address then change gen_exception_err()
to use it.
The gen_exception() and gen_exception_nip() functions are similar so
remove code duplication from those too while at it.
Suggested-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/translate.c | 28 +++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 28fc7791af..d87aae0cc4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -296,33 +296,26 @@ static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
tcg_gen_movi_tl(cpu_nip, nip);
}
-static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
+static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp,
+ uint32_t error, target_ulong nip)
{
TCGv_i32 t0, t1;
- /*
- * These are all synchronous exceptions, we set the PC back to the
- * faulting instruction
- */
- gen_update_nip(ctx, ctx->cia);
+ gen_update_nip(ctx, nip);
t0 = tcg_constant_i32(excp);
t1 = tcg_constant_i32(error);
gen_helper_raise_exception_err(tcg_env, t0, t1);
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception(DisasContext *ctx, uint32_t excp)
+static inline void gen_exception_err(DisasContext *ctx, uint32_t excp,
+ uint32_t error)
{
- TCGv_i32 t0;
-
/*
* These are all synchronous exceptions, we set the PC back to the
* faulting instruction
*/
- gen_update_nip(ctx, ctx->cia);
- t0 = tcg_constant_i32(excp);
- gen_helper_raise_exception(tcg_env, t0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_exception_err_nip(ctx, excp, error, ctx->cia);
}
static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
@@ -336,6 +329,15 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
ctx->base.is_jmp = DISAS_NORETURN;
}
+static inline void gen_exception(DisasContext *ctx, uint32_t excp)
+{
+ /*
+ * These are all synchronous exceptions, we set the PC back to the
+ * faulting instruction
+ */
+ gen_exception_nip(ctx, excp, ctx->cia);
+}
+
#if !defined(CONFIG_USER_ONLY)
static void gen_ppc_maybe_interrupt(DisasContext *ctx)
{
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
` (2 preceding siblings ...)
2024-02-27 15:08 ` [PATCH v7 03/10] target/ppc: Add gen_exception_err_nip() function BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-03-12 12:29 ` Nicholas Piggin
2024-03-12 16:40 ` Nicholas Piggin
2024-02-27 15:08 ` [PATCH v7 05/10] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
` (5 subsequent siblings)
9 siblings, 2 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
Most exceptions are raised with nip pointing to the faulting
instruction but the sc instruction generating a syscall exception
leaves nip pointing to next instruction. Fix gen_sc to not use
gen_exception_err() which sets nip back but correctly set nip to
pc_next so we don't have to patch this in the exception handlers.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/excp_helper.c | 43 ++--------------------------------------
target/ppc/translate.c | 6 ++----
2 files changed, 4 insertions(+), 45 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index fba6e03d18..f1e62d9878 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -116,7 +116,7 @@ static void dump_syscall(CPUPPCState *env)
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
- ppc_dump_gpr(env, 8), env->nip);
+ ppc_dump_gpr(env, 8), env->nip - 4);
}
static void dump_hcall(CPUPPCState *env)
@@ -131,7 +131,7 @@ static void dump_hcall(CPUPPCState *env)
ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
- env->nip);
+ env->nip - 4);
}
#ifdef CONFIG_TCG
@@ -516,12 +516,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
dump_syscall(env);
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
break;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
trace_ppc_excp_print("FIT");
@@ -632,12 +626,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
dump_syscall(env);
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_DECR: /* Decrementer exception */
@@ -780,13 +768,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
} else {
dump_syscall(env);
}
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
-
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
@@ -932,13 +913,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
} else {
dump_syscall(env);
}
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
-
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
@@ -1098,12 +1072,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
dump_syscall(env);
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
@@ -1427,13 +1395,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
} else {
dump_syscall(env);
}
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
-
/* "PAPR mode" built-in hypercall emulation */
if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
PPCVirtualHypervisorClass *vhc =
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d87aae0cc4..a3ac8c3d0e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4575,15 +4575,13 @@ static void gen_hrfid(DisasContext *ctx)
#endif
static void gen_sc(DisasContext *ctx)
{
- uint32_t lev;
-
/*
* LEV is a 7-bit field, but the top 6 bits are treated as a reserved
* field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
* for Ultravisor which TCG does not support, so just ignore the top 6.
*/
- lev = (ctx->opcode >> 5) & 0x1;
- gen_exception_err(ctx, POWERPC_SYSCALL, lev);
+ uint32_t lev = (ctx->opcode >> 5) & 0x1;
+ gen_exception_err_nip(ctx, POWERPC_SYSCALL, lev, ctx->base.pc_next);
}
#if defined(TARGET_PPC64)
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 05/10] target/ppc: Move patching nip from exception handler to helper_scv
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
` (3 preceding siblings ...)
2024-02-27 15:08 ` [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 06/10] target/ppc: Simplify syscall exception handlers BALATON Zoltan
` (4 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
From: Nicholas Piggin <npiggin@gmail.com>
Unlike sc, for scv a facility unavailable interrupt must be generated
if FSCR[SCV]=0 so we can't raise the exception with nip set to next
instruction but we can move advancing nip if the FSCR check passes to
helper_scv so the exception handler does not need to change it.
[balaton: added commit message]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
target/ppc/excp_helper.c | 2 +-
target/ppc/translate.c | 6 +++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f1e62d9878..6cf4542e7e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1414,7 +1414,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
lev = env->error_code;
dump_syscall(env);
- env->nip += 4;
new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
@@ -2537,6 +2536,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env)
void helper_scv(CPUPPCState *env, uint32_t lev)
{
if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
+ env->nip += 4;
raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev);
} else {
raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a3ac8c3d0e..1d69283c80 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4590,7 +4590,11 @@ static void gen_scv(DisasContext *ctx)
{
uint32_t lev = (ctx->opcode >> 5) & 0x7F;
- /* Set the PC back to the faulting instruction. */
+ /*
+ * Set the PC back to the scv instruction (unlike sc), because a facility
+ * unavailable interrupt must be generated if FSCR[SCV]=0. The helper
+ * advances nip if the FSCR check passes.
+ */
gen_update_nip(ctx, ctx->cia);
gen_helper_scv(tcg_env, tcg_constant_i32(lev));
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 06/10] target/ppc: Simplify syscall exception handlers
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
` (4 preceding siblings ...)
2024-02-27 15:08 ` [PATCH v7 05/10] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 07/10] target/ppc: Clean up ifdefs in excp_helper.c, part 1 BALATON Zoltan
` (3 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
After previous changes the hypercall handling in 7xx and 74xx
exception handlers can be folded into one if statement to simplify
this code. Also add "unlikely" to mark the less frequently used branch
for the compiler.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/excp_helper.c | 22 ++++++----------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6cf4542e7e..320835bc74 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -762,26 +762,21 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SYSCALL: /* System call exception */
{
int lev = env->error_code;
-
- if (lev == 1 && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
* uses VOF and the 7xx CPUs, so although the 7xx don't have
* HV mode, we need to keep hypercall support.
*/
- if (lev == 1 && cpu->vhyp) {
+ if (unlikely(lev == 1 && cpu->vhyp)) {
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ dump_hcall(env);
vhc->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
return;
}
-
+ dump_syscall(env);
break;
}
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
@@ -907,26 +902,21 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SYSCALL: /* System call exception */
{
int lev = env->error_code;
-
- if (lev == 1 && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
/*
* The Virtual Open Firmware (VOF) relies on the 'sc 1'
* instruction to communicate with QEMU. The pegasos2 machine
* uses VOF and the 74xx CPUs, so although the 74xx don't have
* HV mode, we need to keep hypercall support.
*/
- if (lev == 1 && cpu->vhyp) {
+ if (unlikely(lev == 1 && cpu->vhyp)) {
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ dump_hcall(env);
vhc->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
return;
}
-
+ dump_syscall(env);
break;
}
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 07/10] target/ppc: Clean up ifdefs in excp_helper.c, part 1
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
` (5 preceding siblings ...)
2024-02-27 15:08 ` [PATCH v7 06/10] target/ppc: Simplify syscall exception handlers BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 08/10] target/ppc: Clean up ifdefs in excp_helper.c, part 2 BALATON Zoltan
` (2 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
Use #ifdef, #ifndef for brevity and add comments to #endif that are
more than a few lines apart for clarity.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/excp_helper.c | 49 ++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 25 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 320835bc74..ba0620ffd1 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -35,7 +35,7 @@
/*****************************************************************************/
/* Exception processing */
-#if !defined(CONFIG_USER_ONLY)
+#ifndef CONFIG_USER_ONLY
static const char *powerpc_excp_name(int excp)
{
@@ -186,7 +186,7 @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
env->error_code);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
static int powerpc_reset_wakeup(CPUPPCState *env, int excp, target_ulong *msr)
{
/* We no longer are in a PM state */
@@ -380,7 +380,7 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr,
}
}
}
-#endif
+#endif /* TARGET_PPC64 */
static void powerpc_reset_excp_state(PowerPCCPU *cpu)
{
@@ -1121,7 +1121,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
/* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
new_msr |= (target_ulong)1 << MSR_CM;
@@ -1544,7 +1544,7 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
g_assert_not_reached();
}
-#endif
+#endif /* TARGET_PPC64 */
static void powerpc_excp(PowerPCCPU *cpu, int excp)
{
@@ -1595,7 +1595,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
powerpc_excp(cpu, cs->exception_index);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
#define P7_UNUSED_INTERRUPTS \
(PPC_INTERRUPT_RESET | PPC_INTERRUPT_HVIRT | PPC_INTERRUPT_CEXT | \
PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
@@ -1926,7 +1926,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
return 0;
}
-#endif
+#endif /* TARGET_PPC64 */
static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
{
@@ -2043,7 +2043,7 @@ static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
static int ppc_next_unmasked_interrupt(CPUPPCState *env)
{
switch (env->excp_model) {
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
case POWERPC_EXCP_POWER7:
return p7_next_unmasked_interrupt(env);
case POWERPC_EXCP_POWER8:
@@ -2082,7 +2082,7 @@ void ppc_maybe_interrupt(CPUPPCState *env)
}
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
static void p7_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
@@ -2284,7 +2284,7 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
interrupt);
}
}
-#endif
+#endif /* TARGET_PPC64 */
static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
{
@@ -2393,7 +2393,7 @@ static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
{
switch (env->excp_model) {
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
case POWERPC_EXCP_POWER7:
p7_deliver_interrupt(env, interrupt);
break;
@@ -2503,9 +2503,9 @@ void helper_raise_exception(CPUPPCState *env, uint32_t exception)
{
raise_exception_err_ra(env, exception, 0, 0);
}
-#endif
+#endif /* CONFIG_TCG */
-#if !defined(CONFIG_USER_ONLY)
+#ifndef CONFIG_USER_ONLY
#ifdef CONFIG_TCG
void helper_store_msr(CPUPPCState *env, target_ulong val)
{
@@ -2522,7 +2522,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env)
ppc_maybe_interrupt(env);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_scv(CPUPPCState *env, uint32_t lev)
{
if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
@@ -2551,7 +2551,7 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn)
ppc_maybe_interrupt(env);
}
-#endif /* defined(TARGET_PPC64) */
+#endif /* TARGET_PPC64 */
static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
{
@@ -2562,7 +2562,7 @@ static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
if (env->flags & POWERPC_FLAG_TGPR)
msr &= ~(1ULL << MSR_TGPR);
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
/* Switching to 32-bit ? Crop the nip */
if (!msr_is_64bit(env, msr)) {
nip = (uint32_t)nip;
@@ -2591,7 +2591,7 @@ void helper_rfi(CPUPPCState *env)
do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_rfid(CPUPPCState *env)
{
/*
@@ -2612,7 +2612,7 @@ void helper_hrfid(CPUPPCState *env)
{
do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
}
-#endif
+#endif /* TARGET_PPC64 */
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
void helper_rfebb(CPUPPCState *env, target_ulong s)
@@ -2689,7 +2689,7 @@ void raise_ebb_perfm_exception(CPUPPCState *env)
do_ebb(env, POWERPC_EXCP_PERFM_EBB);
}
-#endif
+#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
@@ -2731,7 +2731,7 @@ void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
}
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
uint32_t flags)
{
@@ -2744,8 +2744,8 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
POWERPC_EXCP_TRAP, GETPC());
}
}
-#endif
-#endif
+#endif /* TARGET_PPC64 */
+#endif /* CONFIG_TCG */
#ifdef CONFIG_TCG
static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
@@ -2860,8 +2860,7 @@ HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
#endif /* CONFIG_TCG */
-#if !defined(CONFIG_USER_ONLY)
-
+#ifndef CONFIG_USER_ONLY
#ifdef CONFIG_TCG
/* Embedded.Processor Control */
@@ -2970,7 +2969,7 @@ void helper_book3s_msgsnd(target_ulong rb)
book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
{
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP);
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 08/10] target/ppc: Clean up ifdefs in excp_helper.c, part 2
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
` (6 preceding siblings ...)
2024-02-27 15:08 ` [PATCH v7 07/10] target/ppc: Clean up ifdefs in excp_helper.c, part 1 BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 09/10] target/ppc: Clean up ifdefs in excp_helper.c, part 3 BALATON Zoltan
2024-02-27 20:21 ` [PATCH v7 10/10] target/ppc: Remove interrupt handler wrapper functions BALATON Zoltan
9 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
Remove check for !defined(CONFIG_USER_ONLY) as this is already within
an #ifndef CONFIG_USER_ONLY block.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/excp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index ba0620ffd1..8160dabd6a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2614,7 +2614,7 @@ void helper_hrfid(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+#ifdef TARGET_PPC64
void helper_rfebb(CPUPPCState *env, target_ulong s)
{
target_ulong msr = env->msr;
@@ -2689,7 +2689,7 @@ void raise_ebb_perfm_exception(CPUPPCState *env)
do_ebb(env, POWERPC_EXCP_PERFM_EBB);
}
-#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
+#endif /* TARGET_PPC64 */
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 09/10] target/ppc: Clean up ifdefs in excp_helper.c, part 3
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
` (7 preceding siblings ...)
2024-02-27 15:08 ` [PATCH v7 08/10] target/ppc: Clean up ifdefs in excp_helper.c, part 2 BALATON Zoltan
@ 2024-02-27 15:08 ` BALATON Zoltan
2024-02-27 20:21 ` [PATCH v7 10/10] target/ppc: Remove interrupt handler wrapper functions BALATON Zoltan
9 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 15:08 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
Concatenate #if blocks that are ending then beginning on the next line
again.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/excp_helper.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8160dabd6a..f5e1e641ac 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2503,10 +2503,8 @@ void helper_raise_exception(CPUPPCState *env, uint32_t exception)
{
raise_exception_err_ra(env, exception, 0, 0);
}
-#endif /* CONFIG_TCG */
#ifndef CONFIG_USER_ONLY
-#ifdef CONFIG_TCG
void helper_store_msr(CPUPPCState *env, target_ulong val)
{
uint32_t excp = hreg_store_msr(env, val, 0);
@@ -2612,9 +2610,7 @@ void helper_hrfid(CPUPPCState *env)
{
do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
}
-#endif /* TARGET_PPC64 */
-#ifdef TARGET_PPC64
void helper_rfebb(CPUPPCState *env, target_ulong s)
{
target_ulong msr = env->msr;
@@ -2714,10 +2710,8 @@ void helper_rfmci(CPUPPCState *env)
/* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
}
-#endif /* CONFIG_TCG */
-#endif /* !defined(CONFIG_USER_ONLY) */
+#endif /* !CONFIG_USER_ONLY */
-#ifdef CONFIG_TCG
void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
uint32_t flags)
{
@@ -2745,9 +2739,7 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
}
}
#endif /* TARGET_PPC64 */
-#endif /* CONFIG_TCG */
-#ifdef CONFIG_TCG
static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
{
const uint16_t c = 0xfffc;
@@ -2858,11 +2850,8 @@ HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE)
HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
-#endif /* CONFIG_TCG */
#ifndef CONFIG_USER_ONLY
-#ifdef CONFIG_TCG
-
/* Embedded.Processor Control */
static int dbell2irq(target_ulong rb)
{
@@ -3209,5 +3198,5 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
return false;
}
-#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers
2024-02-27 15:08 ` [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers BALATON Zoltan
@ 2024-02-27 15:32 ` Peter Maydell
2024-02-27 16:51 ` BALATON Zoltan
0 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2024-02-27 15:32 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
clg
On Tue, 27 Feb 2024 at 15:10, BALATON Zoltan <balaton@eik.bme.hu> wrote:
>
> Improve readability by shortening some long comments, removing
> comments that state the obvious and dropping some empty lines so they
> don't distract when reading the code.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> Acked-by: Nicholas Piggin <npiggin@gmail.com>
> - /*
> - * new interrupt handler msr preserves existing ME unless
> - * explicitly overridden.
> - */
> + /* new interrupt handler msr preserves ME unless explicitly overriden */
Minor typo introduced here: should be "overridden".
> new_msr = env->msr & (((target_ulong)1 << MSR_ME));
> @@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
> /* new srr1 value excluding must-be-zero bits */
> msr = env->msr & ~0x783f0000ULL;
>
> - /*
> - * new interrupt handler msr preserves existing ME unless
> - * explicitly overridden
> - */
> + /* new interrupt handler msr preserves ME unless explicitly overriden */
Ditto, and similarly for other instances later in the patch.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers
2024-02-27 15:32 ` Peter Maydell
@ 2024-02-27 16:51 ` BALATON Zoltan
2024-02-27 20:24 ` BALATON Zoltan
0 siblings, 1 reply; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 16:51 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, qemu-ppc, Nicholas Piggin, Daniel Henrique Barboza,
clg
On Tue, 27 Feb 2024, Peter Maydell wrote:
> On Tue, 27 Feb 2024 at 15:10, BALATON Zoltan <balaton@eik.bme.hu> wrote:
>>
>> Improve readability by shortening some long comments, removing
>> comments that state the obvious and dropping some empty lines so they
>> don't distract when reading the code.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> Acked-by: Nicholas Piggin <npiggin@gmail.com>
>
>
>> - /*
>> - * new interrupt handler msr preserves existing ME unless
>> - * explicitly overridden.
>> - */
>> + /* new interrupt handler msr preserves ME unless explicitly overriden */
>
> Minor typo introduced here: should be "overridden".
>
>> new_msr = env->msr & (((target_ulong)1 << MSR_ME));
>
>> @@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>> /* new srr1 value excluding must-be-zero bits */
>> msr = env->msr & ~0x783f0000ULL;
>>
>> - /*
>> - * new interrupt handler msr preserves existing ME unless
>> - * explicitly overridden
>> - */
>> + /* new interrupt handler msr preserves ME unless explicitly overriden */
>
> Ditto, and similarly for other instances later in the patch.
Huh, sorry, don't know how I've lost that letter. It also seems that the
last patch gone missing from the series somehow so if it does not turn up,
I can resend it with these fixed.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v7 10/10] target/ppc: Remove interrupt handler wrapper functions
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
` (8 preceding siblings ...)
2024-02-27 15:08 ` [PATCH v7 09/10] target/ppc: Clean up ifdefs in excp_helper.c, part 3 BALATON Zoltan
@ 2024-02-27 20:21 ` BALATON Zoltan
9 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 20:21 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Nicholas Piggin, Daniel Henrique Barboza, clg
These wrappers call out to handle POWER7 and newer in separate
functions but reduce to the generic case when TARGET_PPC64 is not
defined. It is easy enough to include the switch in the beginning of
the generic functions to branch out to the specific functions and get
rid of these wrappers. This avoids one indirection and entirely
compiles out the switch without TARGET_PPC64.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/excp_helper.c | 67 +++++++++++++++++-----------------------
1 file changed, 28 insertions(+), 39 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f5e1e641ac..efb8082348 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1928,8 +1928,21 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
+static int ppc_next_unmasked_interrupt(CPUPPCState *env)
{
+#ifdef TARGET_PPC64
+ switch (env->excp_model) {
+ case POWERPC_EXCP_POWER7:
+ return p7_next_unmasked_interrupt(env);
+ case POWERPC_EXCP_POWER8:
+ return p8_next_unmasked_interrupt(env);
+ case POWERPC_EXCP_POWER9:
+ case POWERPC_EXCP_POWER10:
+ return p9_next_unmasked_interrupt(env);
+ default:
+ break;
+ }
+#endif
bool async_deliver;
/* External reset */
@@ -2040,23 +2053,6 @@ static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
return 0;
}
-static int ppc_next_unmasked_interrupt(CPUPPCState *env)
-{
- switch (env->excp_model) {
-#ifdef TARGET_PPC64
- case POWERPC_EXCP_POWER7:
- return p7_next_unmasked_interrupt(env);
- case POWERPC_EXCP_POWER8:
- return p8_next_unmasked_interrupt(env);
- case POWERPC_EXCP_POWER9:
- case POWERPC_EXCP_POWER10:
- return p9_next_unmasked_interrupt(env);
-#endif
- default:
- return ppc_next_unmasked_interrupt_generic(env);
- }
-}
-
/*
* Sets CPU_INTERRUPT_HARD if there is at least one unmasked interrupt to be
* delivered and clears CPU_INTERRUPT_HARD otherwise.
@@ -2286,8 +2282,21 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
}
#endif /* TARGET_PPC64 */
-static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
+static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
{
+#ifdef TARGET_PPC64
+ switch (env->excp_model) {
+ case POWERPC_EXCP_POWER7:
+ return p7_deliver_interrupt(env, interrupt);
+ case POWERPC_EXCP_POWER8:
+ return p8_deliver_interrupt(env, interrupt);
+ case POWERPC_EXCP_POWER9:
+ case POWERPC_EXCP_POWER10:
+ return p9_deliver_interrupt(env, interrupt);
+ default:
+ break;
+ }
+#endif
PowerPCCPU *cpu = env_archcpu(env);
switch (interrupt) {
@@ -2390,26 +2399,6 @@ static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
}
}
-static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
-{
- switch (env->excp_model) {
-#ifdef TARGET_PPC64
- case POWERPC_EXCP_POWER7:
- p7_deliver_interrupt(env, interrupt);
- break;
- case POWERPC_EXCP_POWER8:
- p8_deliver_interrupt(env, interrupt);
- break;
- case POWERPC_EXCP_POWER9:
- case POWERPC_EXCP_POWER10:
- p9_deliver_interrupt(env, interrupt);
- break;
-#endif
- default:
- ppc_deliver_interrupt_generic(env, interrupt);
- }
-}
-
void ppc_cpu_do_system_reset(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
--
2.30.9
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers
2024-02-27 16:51 ` BALATON Zoltan
@ 2024-02-27 20:24 ` BALATON Zoltan
2024-02-29 3:04 ` Nicholas Piggin
0 siblings, 1 reply; 19+ messages in thread
From: BALATON Zoltan @ 2024-02-27 20:24 UTC (permalink / raw)
To: Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Peter Maydell, Daniel Henrique Barboza, clg
On Tue, 27 Feb 2024, BALATON Zoltan wrote:
> On Tue, 27 Feb 2024, Peter Maydell wrote:
>> On Tue, 27 Feb 2024 at 15:10, BALATON Zoltan <balaton@eik.bme.hu> wrote:
>>>
>>> Improve readability by shortening some long comments, removing
>>> comments that state the obvious and dropping some empty lines so they
>>> don't distract when reading the code.
>>>
>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>> Acked-by: Nicholas Piggin <npiggin@gmail.com>
>>
>>
>>> - /*
>>> - * new interrupt handler msr preserves existing ME unless
>>> - * explicitly overridden.
>>> - */
>>> + /* new interrupt handler msr preserves ME unless explicitly overriden
>>> */
>>
>> Minor typo introduced here: should be "overridden".
>>
>>> new_msr = env->msr & (((target_ulong)1 << MSR_ME));
>>
>>> @@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int
>>> excp)
>>> /* new srr1 value excluding must-be-zero bits */
>>> msr = env->msr & ~0x783f0000ULL;
>>>
>>> - /*
>>> - * new interrupt handler msr preserves existing ME unless
>>> - * explicitly overridden
>>> - */
>>> + /* new interrupt handler msr preserves ME unless explicitly overriden
>>> */
>>
>> Ditto, and similarly for other instances later in the patch.
>
> Huh, sorry, don't know how I've lost that letter. It also seems that the last
> patch gone missing from the series somehow so if it does not turn up, I can
> resend it with these fixed.
As the last patch did not turn up I've resent just that to complete this
v7 series. Do I need to send v8 or if these typos are the only change
needed maybe they could be fixed up during merge.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers
2024-02-27 20:24 ` BALATON Zoltan
@ 2024-02-29 3:04 ` Nicholas Piggin
2024-03-09 11:35 ` BALATON Zoltan
0 siblings, 1 reply; 19+ messages in thread
From: Nicholas Piggin @ 2024-02-29 3:04 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-ppc, Peter Maydell, Daniel Henrique Barboza, clg
On Wed Feb 28, 2024 at 6:24 AM AEST, BALATON Zoltan wrote:
> On Tue, 27 Feb 2024, BALATON Zoltan wrote:
> > On Tue, 27 Feb 2024, Peter Maydell wrote:
> >> On Tue, 27 Feb 2024 at 15:10, BALATON Zoltan <balaton@eik.bme.hu> wrote:
> >>>
> >>> Improve readability by shortening some long comments, removing
> >>> comments that state the obvious and dropping some empty lines so they
> >>> don't distract when reading the code.
> >>>
> >>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> >>> Acked-by: Nicholas Piggin <npiggin@gmail.com>
> >>
> >>
> >>> - /*
> >>> - * new interrupt handler msr preserves existing ME unless
> >>> - * explicitly overridden.
> >>> - */
> >>> + /* new interrupt handler msr preserves ME unless explicitly overriden
> >>> */
> >>
> >> Minor typo introduced here: should be "overridden".
> >>
> >>> new_msr = env->msr & (((target_ulong)1 << MSR_ME));
> >>
> >>> @@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int
> >>> excp)
> >>> /* new srr1 value excluding must-be-zero bits */
> >>> msr = env->msr & ~0x783f0000ULL;
> >>>
> >>> - /*
> >>> - * new interrupt handler msr preserves existing ME unless
> >>> - * explicitly overridden
> >>> - */
> >>> + /* new interrupt handler msr preserves ME unless explicitly overriden
> >>> */
> >>
> >> Ditto, and similarly for other instances later in the patch.
> >
> > Huh, sorry, don't know how I've lost that letter. It also seems that the last
> > patch gone missing from the series somehow so if it does not turn up, I can
> > resend it with these fixed.
>
> As the last patch did not turn up I've resent just that to complete this
> v7 series. Do I need to send v8 or if these typos are the only change
> needed maybe they could be fixed up during merge.
I should be okay to do it.
Thanks,
Nick
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers
2024-02-29 3:04 ` Nicholas Piggin
@ 2024-03-09 11:35 ` BALATON Zoltan
0 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-03-09 11:35 UTC (permalink / raw)
To: Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Peter Maydell, Daniel Henrique Barboza, clg
On Thu, 29 Feb 2024, Nicholas Piggin wrote:
> On Wed Feb 28, 2024 at 6:24 AM AEST, BALATON Zoltan wrote:
>> On Tue, 27 Feb 2024, BALATON Zoltan wrote:
>>> On Tue, 27 Feb 2024, Peter Maydell wrote:
>>>> On Tue, 27 Feb 2024 at 15:10, BALATON Zoltan <balaton@eik.bme.hu> wrote:
>>>>>
>>>>> Improve readability by shortening some long comments, removing
>>>>> comments that state the obvious and dropping some empty lines so they
>>>>> don't distract when reading the code.
>>>>>
>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>> Acked-by: Nicholas Piggin <npiggin@gmail.com>
>>>>
>>>>
>>>>> - /*
>>>>> - * new interrupt handler msr preserves existing ME unless
>>>>> - * explicitly overridden.
>>>>> - */
>>>>> + /* new interrupt handler msr preserves ME unless explicitly overriden
>>>>> */
>>>>
>>>> Minor typo introduced here: should be "overridden".
>>>>
>>>>> new_msr = env->msr & (((target_ulong)1 << MSR_ME));
>>>>
>>>>> @@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int
>>>>> excp)
>>>>> /* new srr1 value excluding must-be-zero bits */
>>>>> msr = env->msr & ~0x783f0000ULL;
>>>>>
>>>>> - /*
>>>>> - * new interrupt handler msr preserves existing ME unless
>>>>> - * explicitly overridden
>>>>> - */
>>>>> + /* new interrupt handler msr preserves ME unless explicitly overriden
>>>>> */
>>>>
>>>> Ditto, and similarly for other instances later in the patch.
>>>
>>> Huh, sorry, don't know how I've lost that letter. It also seems that the last
>>> patch gone missing from the series somehow so if it does not turn up, I can
>>> resend it with these fixed.
>>
>> As the last patch did not turn up I've resent just that to complete this
>> v7 series. Do I need to send v8 or if these typos are the only change
>> needed maybe they could be fixed up during merge.
>
> I should be okay to do it.
Was this merged then? If not then ping as well.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 03/10] target/ppc: Add gen_exception_err_nip() function
2024-02-27 15:08 ` [PATCH v7 03/10] target/ppc: Add gen_exception_err_nip() function BALATON Zoltan
@ 2024-03-12 12:29 ` Nicholas Piggin
0 siblings, 0 replies; 19+ messages in thread
From: Nicholas Piggin @ 2024-03-12 12:29 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza, clg
On Wed Feb 28, 2024 at 1:08 AM AEST, BALATON Zoltan wrote:
> Add gen_exception_err_nip() that does the same as gen_exception_err()
> but takes the nip as a parameter to allow specifying it instead of
> using the current instruction address then change gen_exception_err()
> to use it.
>
> The gen_exception() and gen_exception_nip() functions are similar so
> remove code duplication from those too while at it.
>
> Suggested-by: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Thanks for doing this one
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/translate.c | 28 +++++++++++++++-------------
> 1 file changed, 15 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 28fc7791af..d87aae0cc4 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -296,33 +296,26 @@ static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
> tcg_gen_movi_tl(cpu_nip, nip);
> }
>
> -static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
> +static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp,
> + uint32_t error, target_ulong nip)
> {
> TCGv_i32 t0, t1;
>
> - /*
> - * These are all synchronous exceptions, we set the PC back to the
> - * faulting instruction
> - */
> - gen_update_nip(ctx, ctx->cia);
> + gen_update_nip(ctx, nip);
> t0 = tcg_constant_i32(excp);
> t1 = tcg_constant_i32(error);
> gen_helper_raise_exception_err(tcg_env, t0, t1);
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> -static void gen_exception(DisasContext *ctx, uint32_t excp)
> +static inline void gen_exception_err(DisasContext *ctx, uint32_t excp,
> + uint32_t error)
> {
> - TCGv_i32 t0;
> -
> /*
> * These are all synchronous exceptions, we set the PC back to the
> * faulting instruction
> */
> - gen_update_nip(ctx, ctx->cia);
> - t0 = tcg_constant_i32(excp);
> - gen_helper_raise_exception(tcg_env, t0);
> - ctx->base.is_jmp = DISAS_NORETURN;
> + gen_exception_err_nip(ctx, excp, error, ctx->cia);
> }
>
> static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> @@ -336,6 +329,15 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> +static inline void gen_exception(DisasContext *ctx, uint32_t excp)
> +{
> + /*
> + * These are all synchronous exceptions, we set the PC back to the
> + * faulting instruction
> + */
> + gen_exception_nip(ctx, excp, ctx->cia);
> +}
> +
> #if !defined(CONFIG_USER_ONLY)
> static void gen_ppc_maybe_interrupt(DisasContext *ctx)
> {
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip
2024-02-27 15:08 ` [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
@ 2024-03-12 12:29 ` Nicholas Piggin
2024-03-12 16:40 ` Nicholas Piggin
1 sibling, 0 replies; 19+ messages in thread
From: Nicholas Piggin @ 2024-03-12 12:29 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza, clg
On Wed Feb 28, 2024 at 1:08 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back but correctly set nip to
> pc_next so we don't have to patch this in the exception handlers.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/excp_helper.c | 43 ++--------------------------------------
> target/ppc/translate.c | 6 ++----
> 2 files changed, 4 insertions(+), 45 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index fba6e03d18..f1e62d9878 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -116,7 +116,7 @@ static void dump_syscall(CPUPPCState *env)
> ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
> ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
> ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
> - ppc_dump_gpr(env, 8), env->nip);
> + ppc_dump_gpr(env, 8), env->nip - 4);
> }
>
> static void dump_hcall(CPUPPCState *env)
> @@ -131,7 +131,7 @@ static void dump_hcall(CPUPPCState *env)
> ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
> ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
> ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
> - env->nip);
> + env->nip - 4);
> }
>
> #ifdef CONFIG_TCG
> @@ -516,12 +516,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> dump_syscall(env);
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> break;
> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> trace_ppc_excp_print("FIT");
> @@ -632,12 +626,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> dump_syscall(env);
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> break;
> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> case POWERPC_EXCP_DECR: /* Decrementer exception */
> @@ -780,13 +768,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> } else {
> dump_syscall(env);
> }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> /*
> * The Virtual Open Firmware (VOF) relies on the 'sc 1'
> * instruction to communicate with QEMU. The pegasos2 machine
> @@ -932,13 +913,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
> } else {
> dump_syscall(env);
> }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> /*
> * The Virtual Open Firmware (VOF) relies on the 'sc 1'
> * instruction to communicate with QEMU. The pegasos2 machine
> @@ -1098,12 +1072,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> dump_syscall(env);
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> break;
> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> @@ -1427,13 +1395,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> } else {
> dump_syscall(env);
> }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> /* "PAPR mode" built-in hypercall emulation */
> if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
> PPCVirtualHypervisorClass *vhc =
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d87aae0cc4..a3ac8c3d0e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4575,15 +4575,13 @@ static void gen_hrfid(DisasContext *ctx)
> #endif
> static void gen_sc(DisasContext *ctx)
> {
> - uint32_t lev;
> -
> /*
> * LEV is a 7-bit field, but the top 6 bits are treated as a reserved
> * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
> * for Ultravisor which TCG does not support, so just ignore the top 6.
> */
> - lev = (ctx->opcode >> 5) & 0x1;
> - gen_exception_err(ctx, POWERPC_SYSCALL, lev);
> + uint32_t lev = (ctx->opcode >> 5) & 0x1;
> + gen_exception_err_nip(ctx, POWERPC_SYSCALL, lev, ctx->base.pc_next);
> }
>
> #if defined(TARGET_PPC64)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip
2024-02-27 15:08 ` [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2024-03-12 12:29 ` Nicholas Piggin
@ 2024-03-12 16:40 ` Nicholas Piggin
1 sibling, 0 replies; 19+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:40 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc; +Cc: Daniel Henrique Barboza, clg
On Wed Feb 28, 2024 at 1:08 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back but correctly set nip to
> pc_next so we don't have to patch this in the exception handlers.
These syscall patches are causing the catch-syscalls test on ppc
user to fail, e.g., https://gitlab.com/npiggin/qemu/-/jobs/6375591392
So I dropped them. I didn't have any time to see why. The rest of
the series are fine though.
Thanks,
Nick
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/excp_helper.c | 43 ++--------------------------------------
> target/ppc/translate.c | 6 ++----
> 2 files changed, 4 insertions(+), 45 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index fba6e03d18..f1e62d9878 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -116,7 +116,7 @@ static void dump_syscall(CPUPPCState *env)
> ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
> ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
> ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
> - ppc_dump_gpr(env, 8), env->nip);
> + ppc_dump_gpr(env, 8), env->nip - 4);
> }
>
> static void dump_hcall(CPUPPCState *env)
> @@ -131,7 +131,7 @@ static void dump_hcall(CPUPPCState *env)
> ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
> ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
> ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
> - env->nip);
> + env->nip - 4);
> }
>
> #ifdef CONFIG_TCG
> @@ -516,12 +516,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> dump_syscall(env);
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> break;
> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> trace_ppc_excp_print("FIT");
> @@ -632,12 +626,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> dump_syscall(env);
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> break;
> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> case POWERPC_EXCP_DECR: /* Decrementer exception */
> @@ -780,13 +768,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> } else {
> dump_syscall(env);
> }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> /*
> * The Virtual Open Firmware (VOF) relies on the 'sc 1'
> * instruction to communicate with QEMU. The pegasos2 machine
> @@ -932,13 +913,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
> } else {
> dump_syscall(env);
> }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> /*
> * The Virtual Open Firmware (VOF) relies on the 'sc 1'
> * instruction to communicate with QEMU. The pegasos2 machine
> @@ -1098,12 +1072,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> dump_syscall(env);
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> break;
> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> @@ -1427,13 +1395,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> } else {
> dump_syscall(env);
> }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> /* "PAPR mode" built-in hypercall emulation */
> if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
> PPCVirtualHypervisorClass *vhc =
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d87aae0cc4..a3ac8c3d0e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4575,15 +4575,13 @@ static void gen_hrfid(DisasContext *ctx)
> #endif
> static void gen_sc(DisasContext *ctx)
> {
> - uint32_t lev;
> -
> /*
> * LEV is a 7-bit field, but the top 6 bits are treated as a reserved
> * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
> * for Ultravisor which TCG does not support, so just ignore the top 6.
> */
> - lev = (ctx->opcode >> 5) & 0x1;
> - gen_exception_err(ctx, POWERPC_SYSCALL, lev);
> + uint32_t lev = (ctx->opcode >> 5) & 0x1;
> + gen_exception_err_nip(ctx, POWERPC_SYSCALL, lev, ctx->base.pc_next);
> }
>
> #if defined(TARGET_PPC64)
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2024-03-12 16:40 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-02-27 15:08 [PATCH v7 00/10] Misc clean ups to target/ppc exception handling BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 01/10] target/ppc: Use env_cpu for cpu_abort in excp_helper BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 02/10] target/ppc: Readability improvements in exception handlers BALATON Zoltan
2024-02-27 15:32 ` Peter Maydell
2024-02-27 16:51 ` BALATON Zoltan
2024-02-27 20:24 ` BALATON Zoltan
2024-02-29 3:04 ` Nicholas Piggin
2024-03-09 11:35 ` BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 03/10] target/ppc: Add gen_exception_err_nip() function BALATON Zoltan
2024-03-12 12:29 ` Nicholas Piggin
2024-02-27 15:08 ` [PATCH v7 04/10] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2024-03-12 12:29 ` Nicholas Piggin
2024-03-12 16:40 ` Nicholas Piggin
2024-02-27 15:08 ` [PATCH v7 05/10] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 06/10] target/ppc: Simplify syscall exception handlers BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 07/10] target/ppc: Clean up ifdefs in excp_helper.c, part 1 BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 08/10] target/ppc: Clean up ifdefs in excp_helper.c, part 2 BALATON Zoltan
2024-02-27 15:08 ` [PATCH v7 09/10] target/ppc: Clean up ifdefs in excp_helper.c, part 3 BALATON Zoltan
2024-02-27 20:21 ` [PATCH v7 10/10] target/ppc: Remove interrupt handler wrapper functions BALATON Zoltan
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).