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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id pv7-20020a17090b3c8700b002a5f44353d2sm11626282pjb.7.2024.05.07.03.06.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 May 2024 03:06:55 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 07 May 2024 20:06:51 +1000 Message-Id: Subject: Re: [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() From: "Nicholas Piggin" To: "BALATON Zoltan" , , Cc: "Daniel Henrique Barboza" X-Mailer: aerc 0.17.0 References: In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote: > Instead of putting a large block of code in an if, invert the > condition and return early to be able to deindent the code block. > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 319 ++++++++++++++++++++-------------------- > 1 file changed, 159 insertions(+), 160 deletions(-) > > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index 28847c32f2..2487b4deff 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -1265,187 +1265,186 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, va= ddr eaddr, > *protp =3D ctx.prot; > *psizep =3D TARGET_PAGE_BITS; > return true; > + } else if (!guest_visible) { > + return false; > } Acked-by: Nicholas Piggin > =20 > - if (guest_visible) { > - log_cpu_state_mask(CPU_LOG_MMU, cs, 0); > - if (type =3D=3D ACCESS_CODE) { > - switch (ret) { > - case -1: > - /* No matches in page tables or TLB */ > - switch (env->mmu_model) { > - case POWERPC_MMU_SOFT_6xx: > - cs->exception_index =3D POWERPC_EXCP_IFTLB; > - env->error_code =3D 1 << 18; > - env->spr[SPR_IMISS] =3D eaddr; > - env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; > - goto tlb_miss; > - case POWERPC_MMU_SOFT_4xx: > - cs->exception_index =3D POWERPC_EXCP_ITLB; > - env->error_code =3D 0; > - env->spr[SPR_40x_DEAR] =3D eaddr; > - env->spr[SPR_40x_ESR] =3D 0x00000000; > - break; > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx)= ; > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_ITLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx,= MMU_DATA_LOAD); > - break; > - case POWERPC_MMU_REAL: > - cpu_abort(cs, "PowerPC in real mode should never rai= se " > - "any MMU exceptions\n"); > - default: > - cpu_abort(cs, "Unknown or invalid MMU model\n"); > - } > + log_cpu_state_mask(CPU_LOG_MMU, cs, 0); > + if (type =3D=3D ACCESS_CODE) { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + switch (env->mmu_model) { > + case POWERPC_MMU_SOFT_6xx: > + cs->exception_index =3D POWERPC_EXCP_IFTLB; > + env->error_code =3D 1 << 18; > + env->spr[SPR_IMISS] =3D eaddr; > + env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; > + goto tlb_miss; > + case POWERPC_MMU_SOFT_4xx: > + cs->exception_index =3D POWERPC_EXCP_ITLB; > + env->error_code =3D 0; > + env->spr[SPR_40x_DEAR] =3D eaddr; > + env->spr[SPR_40x_ESR] =3D 0x00000000; > break; > - case -2: > - /* Access rights violation */ > - cs->exception_index =3D POWERPC_EXCP_ISI; > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->error_code =3D 0; > - } else { > - env->error_code =3D 0x08000000; > - } > + case POWERPC_MMU_BOOKE206: > + booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx); > + /* fall through */ > + case POWERPC_MMU_BOOKE: > + cs->exception_index =3D POWERPC_EXCP_ITLB; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, MMU= _DATA_LOAD); > break; > - case -3: > - /* No execute protection violation */ > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->spr[SPR_BOOKE_ESR] =3D 0x00000000; > - env->error_code =3D 0; > + case POWERPC_MMU_REAL: > + cpu_abort(cs, "PowerPC in real mode should never raise " > + "any MMU exceptions\n"); > + default: > + cpu_abort(cs, "Unknown or invalid MMU model\n"); > + } > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > + (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > + env->error_code =3D 0; > + } else { > + env->error_code =3D 0x08000000; > + } > + break; > + case -3: > + /* No execute protection violation */ > + if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > + (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > + env->spr[SPR_BOOKE_ESR] =3D 0x00000000; > + env->error_code =3D 0; > + } else { > + env->error_code =3D 0x10000000; > + } > + cs->exception_index =3D POWERPC_EXCP_ISI; > + break; > + case -4: > + /* Direct store exception */ > + /* No code fetch is allowed in direct-store areas */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > + (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > + env->error_code =3D 0; > + } else { > + env->error_code =3D 0x10000000; > + } > + break; > + } > + } else { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + switch (env->mmu_model) { > + case POWERPC_MMU_SOFT_6xx: > + if (access_type =3D=3D MMU_DATA_STORE) { > + cs->exception_index =3D POWERPC_EXCP_DSTLB; > + env->error_code =3D 1 << 16; > } else { > - env->error_code =3D 0x10000000; > + cs->exception_index =3D POWERPC_EXCP_DLTLB; > + env->error_code =3D 0; > } > - cs->exception_index =3D POWERPC_EXCP_ISI; > + env->spr[SPR_DMISS] =3D eaddr; > + env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; > + tlb_miss: > + env->error_code |=3D ctx.key << 19; > + env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + > + get_pteg_offset32(cpu, ctx.hash[0]); > + env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + > + get_pteg_offset32(cpu, ctx.hash[1]); > break; > - case -4: > - /* Direct store exception */ > - /* No code fetch is allowed in direct-store areas */ > - cs->exception_index =3D POWERPC_EXCP_ISI; > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->error_code =3D 0; > + case POWERPC_MMU_SOFT_4xx: > + cs->exception_index =3D POWERPC_EXCP_DTLB; > + env->error_code =3D 0; > + env->spr[SPR_40x_DEAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_40x_ESR] =3D 0x00800000; > } else { > - env->error_code =3D 0x10000000; > + env->spr[SPR_40x_ESR] =3D 0x00000000; > } > break; > - } > - } else { > - switch (ret) { > - case -1: > - /* No matches in page tables or TLB */ > - switch (env->mmu_model) { > - case POWERPC_MMU_SOFT_6xx: > - if (access_type =3D=3D MMU_DATA_STORE) { > - cs->exception_index =3D POWERPC_EXCP_DSTLB; > - env->error_code =3D 1 << 16; > - } else { > - cs->exception_index =3D POWERPC_EXCP_DLTLB; > - env->error_code =3D 0; > - } > - env->spr[SPR_DMISS] =3D eaddr; > - env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; > - tlb_miss: > - env->error_code |=3D ctx.key << 19; > - env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + > - get_pteg_offset32(cpu, ctx.hash[0]); > - env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + > - get_pteg_offset32(cpu, ctx.hash[1]); > - break; > - case POWERPC_MMU_SOFT_4xx: > - cs->exception_index =3D POWERPC_EXCP_DTLB; > - env->error_code =3D 0; > - env->spr[SPR_40x_DEAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_40x_ESR] =3D 0x00800000; > - } else { > - env->spr[SPR_40x_ESR] =3D 0x00000000; > - } > - break; > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, access_type= , mmu_idx); > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_DTLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx,= access_type); > - break; > - case POWERPC_MMU_REAL: > - cpu_abort(cs, "PowerPC in real mode should never rai= se " > + case POWERPC_MMU_BOOKE206: > + booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > + /* fall through */ > + case POWERPC_MMU_BOOKE: > + cs->exception_index =3D POWERPC_EXCP_DTLB; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > + break; > + case POWERPC_MMU_REAL: > + cpu_abort(cs, "PowerPC in real mode should never raise " > "any MMU exceptions\n"); > - default: > - cpu_abort(cs, "Unknown or invalid MMU model\n"); > + default: > + cpu_abort(cs, "Unknown or invalid MMU model\n"); > + } > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->error_code =3D 0; > + if (env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx) { > + env->spr[SPR_40x_DEAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_40x_ESR] |=3D 0x00800000; > } > + } else if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > + (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > + } else { > + env->spr[SPR_DAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x0A000000; > + } else { > + env->spr[SPR_DSISR] =3D 0x08000000; > + } > + } > + break; > + case -4: > + /* Direct store exception */ > + switch (type) { > + case ACCESS_FLOAT: > + /* Floating point load/store */ > + cs->exception_index =3D POWERPC_EXCP_ALIGN; > + env->error_code =3D POWERPC_EXCP_ALIGN_FP; > + env->spr[SPR_DAR] =3D eaddr; > break; > - case -2: > - /* Access rights violation */ > + case ACCESS_RES: > + /* lwarx, ldarx or stwcx. */ > cs->exception_index =3D POWERPC_EXCP_DSI; > env->error_code =3D 0; > - if (env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx) { > - env->spr[SPR_40x_DEAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_40x_ESR] |=3D 0x00800000; > - } > - } else if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206))= { > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx,= access_type); > + env->spr[SPR_DAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x06000000; > } else { > - env->spr[SPR_DAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_DSISR] =3D 0x0A000000; > - } else { > - env->spr[SPR_DSISR] =3D 0x08000000; > - } > + env->spr[SPR_DSISR] =3D 0x04000000; > } > break; > - case -4: > - /* Direct store exception */ > - switch (type) { > - case ACCESS_FLOAT: > - /* Floating point load/store */ > - cs->exception_index =3D POWERPC_EXCP_ALIGN; > - env->error_code =3D POWERPC_EXCP_ALIGN_FP; > - env->spr[SPR_DAR] =3D eaddr; > - break; > - case ACCESS_RES: > - /* lwarx, ldarx or stwcx. */ > - cs->exception_index =3D POWERPC_EXCP_DSI; > - env->error_code =3D 0; > - env->spr[SPR_DAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_DSISR] =3D 0x06000000; > - } else { > - env->spr[SPR_DSISR] =3D 0x04000000; > - } > - break; > - case ACCESS_EXT: > - /* eciwx or ecowx */ > - cs->exception_index =3D POWERPC_EXCP_DSI; > - env->error_code =3D 0; > - env->spr[SPR_DAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_DSISR] =3D 0x06100000; > - } else { > - env->spr[SPR_DSISR] =3D 0x04100000; > - } > - break; > - default: > - printf("DSI: invalid exception (%d)\n", ret); > - cs->exception_index =3D POWERPC_EXCP_PROGRAM; > - env->error_code =3D > - POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; > - env->spr[SPR_DAR] =3D eaddr; > - break; > + case ACCESS_EXT: > + /* eciwx or ecowx */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->error_code =3D 0; > + env->spr[SPR_DAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x06100000; > + } else { > + env->spr[SPR_DSISR] =3D 0x04100000; > } > break; > + default: > + printf("DSI: invalid exception (%d)\n", ret); > + cs->exception_index =3D POWERPC_EXCP_PROGRAM; > + env->error_code =3D POWERPC_EXCP_INVAL | POWERPC_EXCP_IN= VAL_INVAL; > + env->spr[SPR_DAR] =3D eaddr; > + break; > } > + break; > } > } > return false;