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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id w6-20020a170902e88600b001e96982c4fbsm9803396plg.118.2024.05.07.04.35.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 May 2024 04:35:09 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 07 May 2024 21:35:04 +1000 Message-Id: From: "Nicholas Piggin" To: "BALATON Zoltan" , , Cc: "Daniel Henrique Barboza" Subject: Re: [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function X-Mailer: aerc 0.17.0 References: In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote: > The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as > pp_check() in mmu_common.c. Rename the latter to ppc_pte_prot() and > merge with ppc_hash32_pp_prot() to remove duplicated code. > > Signed-off-by: BALATON Zoltan > --- > target/ppc/internal.h | 2 +- > target/ppc/mmu-hash32.c | 47 +---------------------------------------- > target/ppc/mmu_common.c | 19 +++++++++-------- > 3 files changed, 12 insertions(+), 56 deletions(-) > > diff --git a/target/ppc/internal.h b/target/ppc/internal.h > index 61c2aadd0d..d7c923b017 100644 > --- a/target/ppc/internal.h > +++ b/target/ppc/internal.h > @@ -255,7 +255,7 @@ static inline int prot_for_access_type(MMUAccessType = access_type) > #ifndef CONFIG_USER_ONLY > =20 > /* PowerPC MMU emulation */ > - > +int ppc_pte_prot(int key, int pp, int nx); Hmm, these were split by 496272a7018. 64 was being split out too at the time, so maybe not immediately obvious they were the same. Good consolidation but can you keep pp in the name? It's taking ppc's PTE[pp] (page protection) field and converting it to QEMU prot value. ppc_hash32_pp_prot is probably fine, 6xx is hash too. and could stay in mmu-hash32.c, so just use that version unchanged? Thanks, Nick > bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, > hwaddr *raddrp, int *psizep, int *protp, > int mmu_idx, bool guest_visible); > diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c > index 3976416840..ee9df351ae 100644 > --- a/target/ppc/mmu-hash32.c > +++ b/target/ppc/mmu-hash32.c > @@ -42,51 +42,6 @@ struct mmu_ctx_hash32 { > int key; /* Access key */ > }; > =20 > -static int ppc_hash32_pp_prot(int key, int pp, int nx) > -{ > - int prot; > - > - if (key =3D=3D 0) { > - switch (pp) { > - case 0x0: > - case 0x1: > - case 0x2: > - prot =3D PAGE_READ | PAGE_WRITE; > - break; > - > - case 0x3: > - prot =3D PAGE_READ; > - break; > - > - default: > - abort(); > - } > - } else { > - switch (pp) { > - case 0x0: > - prot =3D 0; > - break; > - > - case 0x1: > - case 0x3: > - prot =3D PAGE_READ; > - break; > - > - case 0x2: > - prot =3D PAGE_READ | PAGE_WRITE; > - break; > - > - default: > - abort(); > - } > - } > - if (nx =3D=3D 0) { > - prot |=3D PAGE_EXEC; > - } > - > - return prot; > -} > - > static int ppc_hash32_pte_prot(int mmu_idx, > target_ulong sr, ppc_hash_pte32_t pte) > { > @@ -95,7 +50,7 @@ static int ppc_hash32_pte_prot(int mmu_idx, > key =3D !!(mmuidx_pr(mmu_idx) ? (sr & SR32_KP) : (sr & SR32_KS)); > pp =3D pte.pte1 & HPTE32_R_PP; > =20 > - return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX)); > + return ppc_pte_prot(key, pp, !!(sr & SR32_NX)); > } > =20 > static target_ulong hash32_bat_size(int mmu_idx, > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index 41ef174ab4..0ce5c1e841 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -75,22 +75,23 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong va= lue) > /***********************************************************************= ******/ > /* PowerPC MMU emulation */ > =20 > -static int pp_check(int key, int pp, int nx) > +int ppc_pte_prot(int key, int pp, int nx) > { > int access; > =20 > /* Compute access rights */ > - access =3D 0; > if (key =3D=3D 0) { > switch (pp) { > case 0x0: > case 0x1: > case 0x2: > - access |=3D PAGE_WRITE; > - /* fall through */ > + access =3D PAGE_READ | PAGE_WRITE; > + break; > case 0x3: > - access |=3D PAGE_READ; > + access =3D PAGE_READ; > break; > + default: > + g_assert_not_reached(); > } > } else { > switch (pp) { > @@ -104,6 +105,8 @@ static int pp_check(int key, int pp, int nx) > case 0x2: > access =3D PAGE_READ | PAGE_WRITE; > break; > + default: > + g_assert_not_reached(); > } > } > if (nx =3D=3D 0) { > @@ -140,7 +143,7 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, targe= t_ulong pte0, > MMUAccessType access_type) > { > target_ulong ptem, mmask; > - int access, ret, pteh, ptev, pp; > + int ret, pteh, ptev, pp; > =20 > ret =3D -1; > /* Check validity and table match */ > @@ -159,11 +162,9 @@ static int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, targ= et_ulong pte0, > return -3; > } > } > - /* Compute access rights */ > - access =3D pp_check(ctx->key, pp, ctx->nx); > /* Keep the matching PTE information */ > ctx->raddr =3D pte1; > - ctx->prot =3D access; > + ctx->prot =3D ppc_pte_prot(ctx->key, pp, ctx->nx); > ret =3D check_prot(ctx->prot, access_type); > if (ret =3D=3D 0) { > /* Access granted */