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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id w17-20020aa79a11000000b006f4476e078dsm8091122pfj.192.2024.05.07.04.51.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 May 2024 04:51:32 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 07 May 2024 21:51:28 +1000 Message-Id: Cc: "Daniel Henrique Barboza" Subject: Re: [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() From: "Nicholas Piggin" To: "BALATON Zoltan" , , X-Mailer: aerc 0.17.0 References: In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote: > Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to > reduce ppc_jumbo_xlate() further. Nice. > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 180 ++++++++++++++++++++++++++++++---------- > 1 file changed, 138 insertions(+), 42 deletions(-) > > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index 0ce5c1e841..a1f98f8de4 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -1250,6 +1250,137 @@ static void booke206_update_mas_tlb_miss(CPUPPCSt= ate *env, target_ulong address, > env->spr[SPR_BOOKE_MAS0] |=3D env->last_way << MAS0_NV_SHIFT; > } > =20 > +static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, > + MMUAccessType access_type, > + hwaddr *raddrp, int *psizep, int *protp, > + int mmu_idx, bool guest_visible) > +{ > + CPUState *cs =3D CPU(cpu); > + CPUPPCState *env =3D &cpu->env; > + mmu_ctx_t ctx; > + int ret; > + > + if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { > + ret =3D mmubooke206_get_physical_address(env, &ctx, eaddr, acces= s_type, > + mmu_idx); > + } else { > + ret =3D mmubooke_get_physical_address(env, &ctx, eaddr, access_t= ype); > + } > + if (ret =3D=3D 0) { > + *raddrp =3D ctx.raddr; > + *protp =3D ctx.prot; > + *psizep =3D TARGET_PAGE_BITS; > + return true; > + } else if (!guest_visible) { > + return false; > + } > + > + log_cpu_state_mask(CPU_LOG_MMU, cs, 0); > + if (access_type =3D=3D MMU_INST_FETCH) { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + switch (env->mmu_model) { > + case POWERPC_MMU_BOOKE206: > + booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > + /* fall through */ > + case POWERPC_MMU_BOOKE: > + cs->exception_index =3D POWERPC_EXCP_ITLB; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > + break; > + default: > + g_assert_not_reached(); > + } > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + env->error_code =3D 0; > + break; > + case -3: > + /* No execute protection violation */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + env->spr[SPR_BOOKE_ESR] =3D 0; > + env->error_code =3D 0; > + break; > + case -4: > + /* Direct store exception */ > + /* No code fetch is allowed in direct-store areas */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + env->error_code =3D 0; > + break; I don't think BookE has -4 (direct address translation) areas, it's only 6xx by the looks. You could put another patch before this to remove the BOOKE tests from the ret =3D=3D -4 cases, then avoid copying them in here. Otherwise I think it looks okay. Thanks, Nick > + } > + } else { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + switch (env->mmu_model) { > + case POWERPC_MMU_BOOKE206: > + booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > + /* fall through */ > + case POWERPC_MMU_BOOKE: > + cs->exception_index =3D POWERPC_EXCP_DTLB; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > + break; > + default: > + g_assert_not_reached(); > + } > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, access_= type); > + break; > + case -4: > + /* Direct store exception */ > + switch (env->access_type) { > + case ACCESS_FLOAT: > + /* Floating point load/store */ > + cs->exception_index =3D POWERPC_EXCP_ALIGN; > + env->error_code =3D POWERPC_EXCP_ALIGN_FP; > + env->spr[SPR_DAR] =3D eaddr; > + break; > + case ACCESS_RES: > + /* lwarx, ldarx or stwcx. */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->error_code =3D 0; > + env->spr[SPR_DAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x06000000; > + } else { > + env->spr[SPR_DSISR] =3D 0x04000000; > + } > + break; > + case ACCESS_EXT: > + /* eciwx or ecowx */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->error_code =3D 0; > + env->spr[SPR_DAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x06100000; > + } else { > + env->spr[SPR_DSISR] =3D 0x04100000; > + } > + break; > + default: > + printf("DSI: invalid exception (%d)\n", ret); > + cs->exception_index =3D POWERPC_EXCP_PROGRAM; > + env->error_code =3D POWERPC_EXCP_INVAL | POWERPC_EXCP_IN= VAL_INVAL; > + env->spr[SPR_DAR] =3D eaddr; > + break; > + } > + break; > + } > + } > + return false; > +} > + > /* Perform address translation */ > /* TODO: Split this by mmu_model. */ > static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, > @@ -1302,15 +1433,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr= eaddr, > env->spr[SPR_40x_DEAR] =3D eaddr; > env->spr[SPR_40x_ESR] =3D 0x00000000; > break; > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_ITLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > - break; > case POWERPC_MMU_REAL: > cpu_abort(cs, "PowerPC in real mode should never raise " > "any MMU exceptions\n"); > @@ -1321,34 +1443,18 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vadd= r eaddr, > case -2: > /* Access rights violation */ > cs->exception_index =3D POWERPC_EXCP_ISI; > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->error_code =3D 0; > - } else { > - env->error_code =3D 0x08000000; > - } > + env->error_code =3D 0x08000000; > break; > case -3: > /* No execute protection violation */ > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->spr[SPR_BOOKE_ESR] =3D 0x00000000; > - env->error_code =3D 0; > - } else { > - env->error_code =3D 0x10000000; > - } > cs->exception_index =3D POWERPC_EXCP_ISI; > + env->error_code =3D 0x10000000; > break; > case -4: > /* Direct store exception */ > /* No code fetch is allowed in direct-store areas */ > cs->exception_index =3D POWERPC_EXCP_ISI; > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->error_code =3D 0; > - } else { > - env->error_code =3D 0x10000000; > - } > + env->error_code =3D 0x10000000; > break; > } > } else { > @@ -1383,15 +1489,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr= eaddr, > env->spr[SPR_40x_ESR] =3D 0x00000000; > } > break; > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_DTLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > - break; > case POWERPC_MMU_REAL: > cpu_abort(cs, "PowerPC in real mode should never raise " > "any MMU exceptions\n"); > @@ -1408,10 +1505,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr= eaddr, > if (access_type =3D=3D MMU_DATA_STORE) { > env->spr[SPR_40x_ESR] |=3D 0x00800000; > } > - } else if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > } else { > env->spr[SPR_DAR] =3D eaddr; > if (access_type =3D=3D MMU_DATA_STORE) { > @@ -1490,7 +1583,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAc= cessType access_type, > case POWERPC_MMU_32B: > return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp, > psizep, protp, mmu_idx, guest_visible); > - > + case POWERPC_MMU_BOOKE: > + case POWERPC_MMU_BOOKE206: > + return ppc_booke_xlate(cpu, eaddr, access_type, raddrp, > + psizep, protp, mmu_idx, guest_visible); > default: > return ppc_jumbo_xlate(cpu, eaddr, access_type, raddrp, > psizep, protp, mmu_idx, guest_visible);