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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id kj6-20020a17090306c600b001ec48815491sm9910848plb.101.2024.05.07.05.15.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 May 2024 05:15:51 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 07 May 2024 22:15:46 +1000 Message-Id: Cc: "Daniel Henrique Barboza" Subject: Re: [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() From: "Nicholas Piggin" To: "BALATON Zoltan" , , X-Mailer: aerc 0.17.0 References: In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Will review this if we can get -4 case removed... Don't know if I'm too keen on doing the fetch branch first and asymmetric (if vs switch) checking of ret in the fetch vs data cases. I think with -4 case removed things will look much nicer. Thanks, Nick On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote: > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 147 +++++++++++++++------------------------- > 1 file changed, 56 insertions(+), 91 deletions(-) > > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index d61c41d8c9..b76611da80 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -1261,106 +1261,71 @@ static bool ppc_booke_xlate(PowerPCCPU *cpu, vad= dr eaddr, > } > =20 > log_cpu_state_mask(CPU_LOG_MMU, cs, 0); > + env->error_code =3D 0; > + if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206 && ret =3D=3D -1) { > + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx); > + } > if (access_type =3D=3D MMU_INST_FETCH) { > - switch (ret) { > - case -1: > + if (ret =3D=3D -1) { > /* No matches in page tables or TLB */ > - switch (env->mmu_model) { > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_ITLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > - break; > - default: > - g_assert_not_reached(); > - } > - break; > - case -2: > - /* Access rights violation */ > - cs->exception_index =3D POWERPC_EXCP_ISI; > - env->error_code =3D 0; > - break; > - case -3: > - /* No execute protection violation */ > - cs->exception_index =3D POWERPC_EXCP_ISI; > - env->spr[SPR_BOOKE_ESR] =3D 0; > - env->error_code =3D 0; > - break; > - case -4: > - /* Direct store exception */ > - /* No code fetch is allowed in direct-store areas */ > + cs->exception_index =3D POWERPC_EXCP_ITLB; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, access_= type); > + } else { > cs->exception_index =3D POWERPC_EXCP_ISI; > - env->error_code =3D 0; > - break; > - } > - } else { > - switch (ret) { > - case -1: > - /* No matches in page tables or TLB */ > - switch (env->mmu_model) { > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_DTLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > - break; > - default: > - g_assert_not_reached(); > + if (ret =3D=3D -3) { > + /* No execute protection violation */ > + env->spr[SPR_BOOKE_ESR] =3D 0; > } > + } > + return false; > + } > + > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + cs->exception_index =3D POWERPC_EXCP_DTLB; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, access_type= ); > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, access_type= ); > + break; > + case -4: > + /* Direct store exception */ > + env->spr[SPR_DAR] =3D eaddr; > + switch (env->access_type) { > + case ACCESS_FLOAT: > + /* Floating point load/store */ > + cs->exception_index =3D POWERPC_EXCP_ALIGN; > + env->error_code =3D POWERPC_EXCP_ALIGN_FP; > break; > - case -2: > - /* Access rights violation */ > + case ACCESS_RES: > + /* lwarx, ldarx or stwcx. */ > cs->exception_index =3D POWERPC_EXCP_DSI; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, access_= type); > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x06000000; > + } else { > + env->spr[SPR_DSISR] =3D 0x04000000; > + } > break; > - case -4: > - /* Direct store exception */ > - switch (env->access_type) { > - case ACCESS_FLOAT: > - /* Floating point load/store */ > - cs->exception_index =3D POWERPC_EXCP_ALIGN; > - env->error_code =3D POWERPC_EXCP_ALIGN_FP; > - env->spr[SPR_DAR] =3D eaddr; > - break; > - case ACCESS_RES: > - /* lwarx, ldarx or stwcx. */ > - cs->exception_index =3D POWERPC_EXCP_DSI; > - env->error_code =3D 0; > - env->spr[SPR_DAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_DSISR] =3D 0x06000000; > - } else { > - env->spr[SPR_DSISR] =3D 0x04000000; > - } > - break; > - case ACCESS_EXT: > - /* eciwx or ecowx */ > - cs->exception_index =3D POWERPC_EXCP_DSI; > - env->error_code =3D 0; > - env->spr[SPR_DAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_DSISR] =3D 0x06100000; > - } else { > - env->spr[SPR_DSISR] =3D 0x04100000; > - } > - break; > - default: > - printf("DSI: invalid exception (%d)\n", ret); > - cs->exception_index =3D POWERPC_EXCP_PROGRAM; > - env->error_code =3D POWERPC_EXCP_INVAL | POWERPC_EXCP_IN= VAL_INVAL; > - env->spr[SPR_DAR] =3D eaddr; > - break; > + case ACCESS_EXT: > + /* eciwx or ecowx */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x06100000; > + } else { > + env->spr[SPR_DSISR] =3D 0x04100000; > } > break; > + default: > + printf("DSI: invalid exception (%d)\n", ret); > + cs->exception_index =3D POWERPC_EXCP_PROGRAM; > + env->error_code =3D POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_= INVAL; > + break; > } > } > return false;