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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0bad62fesm5938325ad.83.2024.05.08.23.17.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 May 2024 23:17:45 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 09 May 2024 16:17:39 +1000 Message-Id: From: "Nicholas Piggin" To: "BALATON Zoltan" , , Cc: "Daniel Henrique Barboza" Subject: Re: [PATCH v4 25/33] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() X-Mailer: aerc 0.17.0 References: <49e2b7e5a0fb98fd3f8a6d3c0c8ac2a05ebceb7a.1715209155.git.balaton@eik.bme.hu> In-Reply-To: <49e2b7e5a0fb98fd3f8a6d3c0c8ac2a05ebceb7a.1715209155.git.balaton@eik.bme.hu> Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote: > Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to > reduce ppc_jumbo_xlate() further. > Reviewed-by: Nicholas Piggin > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 148 ++++++++++++++++++++++++++-------------- > 1 file changed, 98 insertions(+), 50 deletions(-) > > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index 53ffcc795d..be0565f19c 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -1089,21 +1089,9 @@ static int get_physical_address_wtlb(CPUPPCState *= env, mmu_ctx_t *ctx, > MMUAccessType access_type, int type= , > int mmu_idx) > { > - bool real_mode; > - > - if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE) { > - return mmubooke_get_physical_address(env, &ctx->raddr, &ctx->pro= t, > - eaddr, access_type); > - } else if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { > - return mmubooke206_get_physical_address(env, &ctx->raddr, &ctx->= prot, > - eaddr, access_type, mmu_= idx); > - } > - > - real_mode =3D (type =3D=3D ACCESS_CODE) ? !FIELD_EX64(env->msr, MSR,= IR) > - : !FIELD_EX64(env->msr, MSR, DR); > - if (real_mode && (env->mmu_model =3D=3D POWERPC_MMU_SOFT_6xx || > - env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx || > - env->mmu_model =3D=3D POWERPC_MMU_REAL)) { > + bool real_mode =3D (type =3D=3D ACCESS_CODE) ? !FIELD_EX64(env->msr,= MSR, IR) > + : !FIELD_EX64(env->msr, MSR, = DR); > + if (real_mode) { > ctx->raddr =3D eaddr; > ctx->prot =3D PAGE_RWX; > return 0; > @@ -1113,6 +1101,8 @@ static int get_physical_address_wtlb(CPUPPCState *e= nv, mmu_ctx_t *ctx, > case POWERPC_MMU_SOFT_6xx: > return mmu6xx_get_physical_address(env, ctx, eaddr, access_type,= type); > case POWERPC_MMU_SOFT_4xx: > + /* avoid maybe used uninitialized warnings for unused fields in = ctx */ > + memset(ctx, 0, sizeof(*ctx)); > return mmu40x_get_physical_address(env, &ctx->raddr, &ctx->prot,= eaddr, > access_type); > case POWERPC_MMU_REAL: > @@ -1177,6 +1167,93 @@ static void booke206_update_mas_tlb_miss(CPUPPCSta= te *env, target_ulong address, > env->spr[SPR_BOOKE_MAS0] |=3D env->last_way << MAS0_NV_SHIFT; > } > =20 > +static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, > + MMUAccessType access_type, > + hwaddr *raddrp, int *psizep, int *protp, > + int mmu_idx, bool guest_visible) > +{ > + CPUState *cs =3D CPU(cpu); > + CPUPPCState *env =3D &cpu->env; > + hwaddr raddr; > + int prot, ret; > + > + if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { > + ret =3D mmubooke206_get_physical_address(env, &raddr, &prot, ead= dr, > + access_type, mmu_idx); > + } else { > + ret =3D mmubooke_get_physical_address(env, &raddr, &prot, eaddr, > + access_type); > + } > + if (ret =3D=3D 0) { > + *raddrp =3D raddr; > + *protp =3D prot; > + *psizep =3D TARGET_PAGE_BITS; > + return true; > + } else if (!guest_visible) { > + return false; > + } > + > + log_cpu_state_mask(CPU_LOG_MMU, cs, 0); > + if (access_type =3D=3D MMU_INST_FETCH) { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + switch (env->mmu_model) { > + case POWERPC_MMU_BOOKE206: > + booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > + /* fall through */ > + case POWERPC_MMU_BOOKE: > + cs->exception_index =3D POWERPC_EXCP_ITLB; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > + break; > + default: > + g_assert_not_reached(); > + } > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + env->error_code =3D 0; > + break; > + case -3: > + /* No execute protection violation */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + env->spr[SPR_BOOKE_ESR] =3D 0; > + env->error_code =3D 0; > + break; > + } > + } else { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + switch (env->mmu_model) { > + case POWERPC_MMU_BOOKE206: > + booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > + /* fall through */ > + case POWERPC_MMU_BOOKE: > + cs->exception_index =3D POWERPC_EXCP_DTLB; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > + break; > + default: > + g_assert_not_reached(); > + } > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->error_code =3D 0; > + env->spr[SPR_BOOKE_DEAR] =3D eaddr; > + env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, access_= type); > + break; > + } > + } > + return false; > +} > + > /* Perform address translation */ > /* TODO: Split this by mmu_model. */ > static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, > @@ -1229,15 +1306,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr= eaddr, > env->spr[SPR_40x_DEAR] =3D eaddr; > env->spr[SPR_40x_ESR] =3D 0x00000000; > break; > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_ITLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > - break; > case POWERPC_MMU_REAL: > cpu_abort(cs, "PowerPC in real mode should never raise " > "any MMU exceptions\n"); > @@ -1248,23 +1316,12 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vadd= r eaddr, > case -2: > /* Access rights violation */ > cs->exception_index =3D POWERPC_EXCP_ISI; > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->error_code =3D 0; > - } else { > - env->error_code =3D 0x08000000; > - } > + env->error_code =3D 0x08000000; > break; > case -3: > /* No execute protection violation */ > - if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->spr[SPR_BOOKE_ESR] =3D 0x00000000; > - env->error_code =3D 0; > - } else { > - env->error_code =3D 0x10000000; > - } > cs->exception_index =3D POWERPC_EXCP_ISI; > + env->error_code =3D 0x10000000; > break; > case -4: > /* Direct store exception */ > @@ -1305,15 +1362,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr= eaddr, > env->spr[SPR_40x_ESR] =3D 0x00000000; > } > break; > - case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, eaddr, access_type, mm= u_idx); > - /* fall through */ > - case POWERPC_MMU_BOOKE: > - cs->exception_index =3D POWERPC_EXCP_DTLB; > - env->error_code =3D 0; > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > - break; > case POWERPC_MMU_REAL: > cpu_abort(cs, "PowerPC in real mode should never raise " > "any MMU exceptions\n"); > @@ -1330,10 +1378,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr= eaddr, > if (access_type =3D=3D MMU_DATA_STORE) { > env->spr[SPR_40x_ESR] |=3D 0x00800000; > } > - } else if ((env->mmu_model =3D=3D POWERPC_MMU_BOOKE) || > - (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206)) { > - env->spr[SPR_BOOKE_DEAR] =3D eaddr; > - env->spr[SPR_BOOKE_ESR] =3D mmubooke206_esr(mmu_idx, acc= ess_type); > } else { > env->spr[SPR_DAR] =3D eaddr; > if (access_type =3D=3D MMU_DATA_STORE) { > @@ -1412,6 +1456,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAc= cessType access_type, > case POWERPC_MMU_32B: > return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp, > psizep, protp, mmu_idx, guest_visible); > + case POWERPC_MMU_BOOKE: > + case POWERPC_MMU_BOOKE206: > + return ppc_booke_xlate(cpu, eaddr, access_type, raddrp, > + psizep, protp, mmu_idx, guest_visible); > case POWERPC_MMU_MPC8xx: > cpu_abort(env_cpu(&cpu->env), "MPC8xx MMU model is not implement= ed\n"); > default: