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Thu, 16 May 2024 22:49:19 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 17 May 2024 15:49:13 +1000 Message-Id: Subject: Re: [PATCH v7 25/61] target/ppc/mmu_common.c: Split off 40x cases from ppc_jumbo_xlate() From: "Nicholas Piggin" To: "BALATON Zoltan" , , Cc: "Daniel Henrique Barboza" X-Mailer: aerc 0.17.0 References: In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=npiggin@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote: > Introduce ppc_40x_xlate() to split off 40x handlning leaving only 6xx > in ppc_jumbo_xlate() now. > Reviewed-by: Nicholas Piggin > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 150 +++++++++++++++++++++++++--------------- > 1 file changed, 93 insertions(+), 57 deletions(-) > > diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c > index ab912da821..ddb014e0aa 100644 > --- a/target/ppc/mmu_common.c > +++ b/target/ppc/mmu_common.c > @@ -1258,6 +1258,74 @@ static bool ppc_real_mode_xlate(PowerPCCPU *cpu, v= addr eaddr, > return false; > } > =20 > +static bool ppc_40x_xlate(PowerPCCPU *cpu, vaddr eaddr, > + MMUAccessType access_type, > + hwaddr *raddrp, int *psizep, int *protp, > + int mmu_idx, bool guest_visible) > +{ > + CPUState *cs =3D CPU(cpu); > + CPUPPCState *env =3D &cpu->env; > + int ret; > + > + if (ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psizep, pro= tp)) { > + return true; > + } > + > + ret =3D mmu40x_get_physical_address(env, raddrp, protp, eaddr, acces= s_type); > + if (ret =3D=3D 0) { > + *psizep =3D TARGET_PAGE_BITS; > + return true; > + } else if (!guest_visible) { > + return false; > + } > + > + log_cpu_state_mask(CPU_LOG_MMU, cs, 0); > + if (access_type =3D=3D MMU_INST_FETCH) { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + cs->exception_index =3D POWERPC_EXCP_ITLB; > + env->error_code =3D 0; > + env->spr[SPR_40x_DEAR] =3D eaddr; > + env->spr[SPR_40x_ESR] =3D 0x00000000; > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_ISI; > + env->error_code =3D 0x08000000; > + break; > + default: > + g_assert_not_reached(); > + } > + } else { > + switch (ret) { > + case -1: > + /* No matches in page tables or TLB */ > + cs->exception_index =3D POWERPC_EXCP_DTLB; > + env->error_code =3D 0; > + env->spr[SPR_40x_DEAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_40x_ESR] =3D 0x00800000; > + } else { > + env->spr[SPR_40x_ESR] =3D 0x00000000; > + } > + break; > + case -2: > + /* Access rights violation */ > + cs->exception_index =3D POWERPC_EXCP_DSI; > + env->error_code =3D 0; > + env->spr[SPR_40x_DEAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_40x_ESR] |=3D 0x00800000; > + } > + break; > + default: > + g_assert_not_reached(); > + } > + } > + return false; > +} > + > /* Perform address translation */ > /* TODO: Split this by mmu_model. */ > static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, > @@ -1301,23 +1369,11 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vadd= r eaddr, > switch (ret) { > case -1: > /* No matches in page tables or TLB */ > - switch (env->mmu_model) { > - case POWERPC_MMU_SOFT_6xx: > - cs->exception_index =3D POWERPC_EXCP_IFTLB; > - env->error_code =3D 1 << 18; > - env->spr[SPR_IMISS] =3D eaddr; > - env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; > - goto tlb_miss; > - case POWERPC_MMU_SOFT_4xx: > - cs->exception_index =3D POWERPC_EXCP_ITLB; > - env->error_code =3D 0; > - env->spr[SPR_40x_DEAR] =3D eaddr; > - env->spr[SPR_40x_ESR] =3D 0x00000000; > - break; > - default: > - g_assert_not_reached(); > - } > - break; > + cs->exception_index =3D POWERPC_EXCP_IFTLB; > + env->error_code =3D 1 << 18; > + env->spr[SPR_IMISS] =3D eaddr; > + env->spr[SPR_ICMP] =3D 0x80000000 | ctx.ptem; > + goto tlb_miss; > case -2: > /* Access rights violation */ > cs->exception_index =3D POWERPC_EXCP_ISI; > @@ -1339,54 +1395,31 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vadd= r eaddr, > switch (ret) { > case -1: > /* No matches in page tables or TLB */ > - switch (env->mmu_model) { > - case POWERPC_MMU_SOFT_6xx: > - if (access_type =3D=3D MMU_DATA_STORE) { > - cs->exception_index =3D POWERPC_EXCP_DSTLB; > - env->error_code =3D 1 << 16; > - } else { > - cs->exception_index =3D POWERPC_EXCP_DLTLB; > - env->error_code =3D 0; > - } > - env->spr[SPR_DMISS] =3D eaddr; > - env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; > - tlb_miss: > - env->error_code |=3D ctx.key << 19; > - env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + > - get_pteg_offset32(cpu, ctx.hash[0]); > - env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + > - get_pteg_offset32(cpu, ctx.hash[1]); > - break; > - case POWERPC_MMU_SOFT_4xx: > - cs->exception_index =3D POWERPC_EXCP_DTLB; > + if (access_type =3D=3D MMU_DATA_STORE) { > + cs->exception_index =3D POWERPC_EXCP_DSTLB; > + env->error_code =3D 1 << 16; > + } else { > + cs->exception_index =3D POWERPC_EXCP_DLTLB; > env->error_code =3D 0; > - env->spr[SPR_40x_DEAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_40x_ESR] =3D 0x00800000; > - } else { > - env->spr[SPR_40x_ESR] =3D 0x00000000; > - } > - break; > - default: > - g_assert_not_reached(); > } > + env->spr[SPR_DMISS] =3D eaddr; > + env->spr[SPR_DCMP] =3D 0x80000000 | ctx.ptem; > +tlb_miss: > + env->error_code |=3D ctx.key << 19; > + env->spr[SPR_HASH1] =3D ppc_hash32_hpt_base(cpu) + > + get_pteg_offset32(cpu, ctx.hash[0]); > + env->spr[SPR_HASH2] =3D ppc_hash32_hpt_base(cpu) + > + get_pteg_offset32(cpu, ctx.hash[1]); > break; > case -2: > /* Access rights violation */ > cs->exception_index =3D POWERPC_EXCP_DSI; > env->error_code =3D 0; > - if (env->mmu_model =3D=3D POWERPC_MMU_SOFT_4xx) { > - env->spr[SPR_40x_DEAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_40x_ESR] |=3D 0x00800000; > - } > + env->spr[SPR_DAR] =3D eaddr; > + if (access_type =3D=3D MMU_DATA_STORE) { > + env->spr[SPR_DSISR] =3D 0x0A000000; > } else { > - env->spr[SPR_DAR] =3D eaddr; > - if (access_type =3D=3D MMU_DATA_STORE) { > - env->spr[SPR_DSISR] =3D 0x0A000000; > - } else { > - env->spr[SPR_DSISR] =3D 0x08000000; > - } > + env->spr[SPR_DSISR] =3D 0x08000000; > } > break; > case -4: > @@ -1462,6 +1495,9 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAcc= essType access_type, > case POWERPC_MMU_BOOKE206: > return ppc_booke_xlate(cpu, eaddr, access_type, raddrp, > psizep, protp, mmu_idx, guest_visible); > + case POWERPC_MMU_SOFT_4xx: > + return ppc_40x_xlate(cpu, eaddr, access_type, raddrp, > + psizep, protp, mmu_idx, guest_visible); > case POWERPC_MMU_REAL: > return ppc_real_mode_xlate(cpu, eaddr, access_type, raddrp, psiz= ep, > protp);