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From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	qemu-ppc@nongnu.org
Cc: "Caleb Schlossin" <calebs@linux.vnet.ibm.com>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	qemu-devel@nongnu.org
Subject: Re: [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well
Date: Thu, 30 May 2024 16:38:26 +1000	[thread overview]
Message-ID: <D1MRTGSNBMIG.UM9QTB7080GH@gmail.com> (raw)
In-Reply-To: <53791846-3b8c-4da8-8cca-c2c521c59450@kaod.org>

On Wed May 29, 2024 at 4:30 PM AEST, Cédric Le Goater wrote:
> On 5/29/24 02:24, Nicholas Piggin wrote:
> > On Tue May 28, 2024 at 6:32 PM AEST, Harsh Prateek Bora wrote:
> >>
> >>
> >> On 5/26/24 17:56, Nicholas Piggin wrote:
> >>> The chip_pir chip class method allows the platform to set the PIR
> >>> processor identification register. Extend this to a more general
> >>> ID function which also allows the TIR to be set. This is in
> >>> preparation for "big core", which is a more complicated topology
> >>> of cores and threads.
> >>>
> >>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> >>> ---
> >>>    include/hw/ppc/pnv_chip.h |  3 +-
> >>>    hw/ppc/pnv.c              | 61 ++++++++++++++++++++++++---------------
> >>>    hw/ppc/pnv_core.c         | 10 ++++---
> >>>    3 files changed, 45 insertions(+), 29 deletions(-)
> >>>
> >>> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> >>> index 8589f3291e..679723926a 100644
> >>> --- a/include/hw/ppc/pnv_chip.h
> >>> +++ b/include/hw/ppc/pnv_chip.h
> >>> @@ -147,7 +147,8 @@ struct PnvChipClass {
> >>>    
> >>>        DeviceRealize parent_realize;
> >>>    
> >>> -    uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id);
> >>> +    void (*processor_id)(PnvChip *chip, uint32_t core_id, uint32_t thread_id,
> >>> +                         uint32_t *pir, uint32_t *tir);
> >>
> >> Should it be named get_chip_core_thread_regs() ?
> > 
> > Yeah, the name isn't great. It is getting the regs, but the regs are the
> > "pervasive id" used as well... but maybe that's not too relevant here.
> > What about we drop chip_ since we have the chip and no other methods use
> > such prefix, then call it get_thread_pir_tir()?
>
> processor relates to chip and so, processor_id() is not great indeed.
> get_pir_tir() would be enough I think.
>
> What would be good though, since pnv is growing, is to start adding
> documentation to these common helpers.

Okay we'll use that name.

You mean just a comment them in the header? Might as well do that for
new ones at least.

Thanks,
Nick


  reply	other threads:[~2024-05-30  6:39 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-26 12:26 [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-05-27 15:23   ` Cédric Le Goater
2024-05-28  6:19   ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-05-28  6:28   ` Harsh Prateek Bora
2024-05-28  7:52     ` Cédric Le Goater
2024-05-29  0:19       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers Nicholas Piggin
2024-05-28  6:50   ` Harsh Prateek Bora
2024-05-29  0:13     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines Nicholas Piggin
2024-05-28  7:10   ` Harsh Prateek Bora
2024-05-28  7:45     ` Cédric Le Goater
2024-05-29  0:18       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-05-28  8:32   ` Harsh Prateek Bora
2024-05-29  0:24     ` Nicholas Piggin
2024-05-29  6:30       ` Cédric Le Goater
2024-05-30  6:38         ` Nicholas Piggin [this message]
2024-05-30  6:42           ` Cédric Le Goater
2024-05-26 12:26 ` [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-05-28  8:48   ` Harsh Prateek Bora
2024-05-28  8:52     ` Harsh Prateek Bora
2024-05-29  0:28       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-05-28  9:16   ` Harsh Prateek Bora
2024-05-29  0:31     ` Nicholas Piggin
2024-05-29  6:34   ` Cédric Le Goater
2024-05-30  6:38     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling Nicholas Piggin
2024-05-29  6:57   ` Cédric Le Goater
2024-05-30  6:52     ` Nicholas Piggin
2024-05-30  7:46       ` Cédric Le Goater
2024-06-03  5:22         ` Nicholas Piggin
2024-05-29 10:49   ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-05-29  7:00   ` Cédric Le Goater
2024-05-30  6:53     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 10/10] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-05-29  7:02   ` Cédric Le Goater
2024-05-27  6:25 ` [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
2024-05-27  7:32   ` Nicholas Piggin
2024-05-27  7:36     ` Cédric Le Goater

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