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Wed, 29 May 2024 23:38:32 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 30 May 2024 16:38:26 +1000 Message-Id: Cc: "Caleb Schlossin" , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Daniel Henrique Barboza" , Subject: Re: [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well From: "Nicholas Piggin" To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Harsh Prateek Bora" , X-Mailer: aerc 0.17.0 References: <20240526122612.473476-1-npiggin@gmail.com> <20240526122612.473476-6-npiggin@gmail.com> <39e4ac93-256b-424b-8ecb-7ed87afeb048@linux.ibm.com> <53791846-3b8c-4da8-8cca-c2c521c59450@kaod.org> In-Reply-To: <53791846-3b8c-4da8-8cca-c2c521c59450@kaod.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed May 29, 2024 at 4:30 PM AEST, C=C3=A9dric Le Goater wrote: > On 5/29/24 02:24, Nicholas Piggin wrote: > > On Tue May 28, 2024 at 6:32 PM AEST, Harsh Prateek Bora wrote: > >> > >> > >> On 5/26/24 17:56, Nicholas Piggin wrote: > >>> The chip_pir chip class method allows the platform to set the PIR > >>> processor identification register. Extend this to a more general > >>> ID function which also allows the TIR to be set. This is in > >>> preparation for "big core", which is a more complicated topology > >>> of cores and threads. > >>> > >>> Signed-off-by: Nicholas Piggin > >>> --- > >>> include/hw/ppc/pnv_chip.h | 3 +- > >>> hw/ppc/pnv.c | 61 ++++++++++++++++++++++++-----------= ---- > >>> hw/ppc/pnv_core.c | 10 ++++--- > >>> 3 files changed, 45 insertions(+), 29 deletions(-) > >>> > >>> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h > >>> index 8589f3291e..679723926a 100644 > >>> --- a/include/hw/ppc/pnv_chip.h > >>> +++ b/include/hw/ppc/pnv_chip.h > >>> @@ -147,7 +147,8 @@ struct PnvChipClass { > >>> =20 > >>> DeviceRealize parent_realize; > >>> =20 > >>> - uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t t= hread_id); > >>> + void (*processor_id)(PnvChip *chip, uint32_t core_id, uint32_t t= hread_id, > >>> + uint32_t *pir, uint32_t *tir); > >> > >> Should it be named get_chip_core_thread_regs() ? > >=20 > > Yeah, the name isn't great. It is getting the regs, but the regs are th= e > > "pervasive id" used as well... but maybe that's not too relevant here. > > What about we drop chip_ since we have the chip and no other methods us= e > > such prefix, then call it get_thread_pir_tir()? > > processor relates to chip and so, processor_id() is not great indeed. > get_pir_tir() would be enough I think. > > What would be good though, since pnv is growing, is to start adding > documentation to these common helpers. Okay we'll use that name. You mean just a comment them in the header? Might as well do that for new ones at least. Thanks, Nick