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Wed, 29 May 2024 23:54:05 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 30 May 2024 16:53:59 +1000 Message-Id: Cc: "Caleb Schlossin" , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Daniel Henrique Barboza" , Subject: Re: [RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls From: "Nicholas Piggin" To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , X-Mailer: aerc 0.17.0 References: <20240526122612.473476-1-npiggin@gmail.com> <20240526122612.473476-10-npiggin@gmail.com> <7f54afb7-3c2c-44b4-bc00-8b24e0ba51e1@kaod.org> In-Reply-To: <7f54afb7-3c2c-44b4-bc00-8b24e0ba51e1@kaod.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed May 29, 2024 at 5:00 PM AEST, C=C3=A9dric Le Goater wrote: > On 5/26/24 14:26, Nicholas Piggin wrote: > > The PC unit in the processor core contains xscom registers that provide > > low level status and control of the CPU. > >=20 > > This implements "direct controls" sufficient for OPAL (skiboot) firmwar= e > > use, which is to stop threads and send them non-maskable IPIs in the > > form of SRESET interrupts. > >=20 > > POWER10 is sufficiently different (particularly QME and special wakeup) > > from POWER9 that it is not trivial to implement by reusing the code. > >=20 > > Signed-off-by: Nicholas Piggin > > --- > > include/hw/core/cpu.h | 8 ++++ > > include/hw/ppc/pnv.h | 2 + > > include/hw/ppc/pnv_core.h | 3 ++ > > hw/ppc/pnv.c | 7 +++- > > hw/ppc/pnv_core.c | 88 ++++++++++++++++++++++++++++++++++++--= - > > system/cpus.c | 10 +++++ > > 6 files changed, 112 insertions(+), 6 deletions(-) > >=20 > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > > index bb398e8237..52a8fc65cb 100644 > > --- a/include/hw/core/cpu.h > > +++ b/include/hw/core/cpu.h > > @@ -974,6 +974,14 @@ void cpu_reset_interrupt(CPUState *cpu, int mask); > > */ > > void cpu_exit(CPUState *cpu); > > =20 > > +/** > > + * cpu_pause: > > + * @cpu: The CPU to pause. > > + * > > + * Resumes CPU, i.e. puts CPU into stopped state. > > + */ > > +void cpu_pause(CPUState *cpu); > > + > > /** > > * cpu_resume: > > * @cpu: The CPU to resume. > > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > > index 93ecb062b4..bec603f1a8 100644 > > --- a/include/hw/ppc/pnv.h > > +++ b/include/hw/ppc/pnv.h > > @@ -111,6 +111,8 @@ PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *ph= b); > > #define PNV_FDT_ADDR 0x01000000 > > #define PNV_TIMEBASE_FREQ 512000000ULL > > =20 > > +void pnv_cpu_do_nmi(CPUState *cs); > > + > > /* > > * BMC helpers > > */ > > diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h > > index 39f8f33e6c..9599da15ea 100644 > > --- a/include/hw/ppc/pnv_core.h > > +++ b/include/hw/ppc/pnv_core.h > > @@ -109,6 +109,9 @@ OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD= ) > > struct PnvQuad { > > DeviceState parent_obj; > > =20 > > + bool special_wakeup_done; > > + bool special_wakeup[4]; > > + > > uint32_t quad_id; > > MemoryRegion xscom_regs; > > MemoryRegion xscom_qme_regs; > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > > index 5364c55bbb..765142965f 100644 > > --- a/hw/ppc/pnv.c > > +++ b/hw/ppc/pnv.c > > @@ -2700,12 +2700,17 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs,= run_on_cpu_data arg) > > } > > } > > =20 > > +void pnv_cpu_do_nmi(CPUState *cs) > > +{ > > + async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); > > +} > > + > > static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) > > { > > CPUState *cs; > > =20 > > CPU_FOREACH(cs) { > > - async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); > > + pnv_cpu_do_nmi(cs); > > } > > } > > What about ? > > https://lore.kernel.org/qemu-devel/20240424093048.180966-1-clg@redhat.com= / I haven't forgotten it. I just didn't put it in the first PR since there was quite a lot of pnv patches to do so I thought I will collect most of them for another PR. Thanks, Nick