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Thu, 04 Jul 2024 00:17:04 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 04 Jul 2024 17:16:59 +1000 Message-Id: Cc: "Daniel Henrique Barboza" Subject: Re: [PATCH 31/43] target/ppc/mmu-radix64: Remove externally unused parts from header From: "Nicholas Piggin" To: "BALATON Zoltan" , , X-Mailer: aerc 0.17.0 References: <3eccbbc40175cbf8e592fb62c0544202052c571c.1716763435.git.balaton@eik.bme.hu> In-Reply-To: <3eccbbc40175cbf8e592fb62c0544202052c571c.1716763435.git.balaton@eik.bme.hu> Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=npiggin@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > Move the parts not needed outside of mmu-radix64.c from the header to > the C file to leave only parts in the header that need to be exported. > Also drop unneded include of this header. > > Signed-off-by: BALATON Zoltan Acked-by: Nicholas Piggin > --- > target/ppc/mmu-book3s-v3.c | 1 - > target/ppc/mmu-radix64.c | 49 +++++++++++++++++++++++++++++++++++ > target/ppc/mmu-radix64.h | 53 +------------------------------------- > 3 files changed, 50 insertions(+), 53 deletions(-) > > diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c > index c8f69b3df9..a812cb5113 100644 > --- a/target/ppc/mmu-book3s-v3.c > +++ b/target/ppc/mmu-book3s-v3.c > @@ -21,7 +21,6 @@ > #include "cpu.h" > #include "mmu-hash64.h" > #include "mmu-book3s-v3.h" > -#include "mmu-radix64.h" > =20 > bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t= *entry) > { > diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c > index 5a02e4963b..cf9619e847 100644 > --- a/target/ppc/mmu-radix64.c > +++ b/target/ppc/mmu-radix64.c > @@ -29,6 +29,37 @@ > #include "mmu-radix64.h" > #include "mmu-book3s-v3.h" > =20 > +/* Radix Partition Table Entry Fields */ > +#define PATE1_R_PRTB 0x0FFFFFFFFFFFF000 > +#define PATE1_R_PRTS 0x000000000000001F > + > +/* Radix Process Table Entry Fields */ > +#define PRTBE_R_GET_RTS(rts) \ > + ((((rts >> 58) & 0x18) | ((rts >> 5) & 0x7)) + 31) > +#define PRTBE_R_RPDB 0x0FFFFFFFFFFFFF00 > +#define PRTBE_R_RPDS 0x000000000000001F > + > +/* Radix Page Directory/Table Entry Fields */ > +#define R_PTE_VALID 0x8000000000000000 > +#define R_PTE_LEAF 0x4000000000000000 > +#define R_PTE_SW0 0x2000000000000000 > +#define R_PTE_RPN 0x01FFFFFFFFFFF000 > +#define R_PTE_SW1 0x0000000000000E00 > +#define R_GET_SW(sw) (((sw >> 58) & 0x8) | ((sw >> 9) & 0x7)) > +#define R_PTE_R 0x0000000000000100 > +#define R_PTE_C 0x0000000000000080 > +#define R_PTE_ATT 0x0000000000000030 > +#define R_PTE_ATT_NORMAL 0x0000000000000000 > +#define R_PTE_ATT_SAO 0x0000000000000010 > +#define R_PTE_ATT_NI_IO 0x0000000000000020 > +#define R_PTE_ATT_TOLERANT_IO 0x0000000000000030 > +#define R_PTE_EAA_PRIV 0x0000000000000008 > +#define R_PTE_EAA_R 0x0000000000000004 > +#define R_PTE_EAA_RW 0x0000000000000002 > +#define R_PTE_EAA_X 0x0000000000000001 > +#define R_PDE_NLB PRTBE_R_RPDB > +#define R_PDE_NLS PRTBE_R_RPDS > + > static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env, > vaddr eaddr, > uint64_t *lpid, uint64_= t *pid) > @@ -180,6 +211,24 @@ static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, M= MUAccessType access_type, > } > } > =20 > +static int ppc_radix64_get_prot_eaa(uint64_t pte) > +{ > + return (pte & R_PTE_EAA_R ? PAGE_READ : 0) | > + (pte & R_PTE_EAA_RW ? PAGE_READ | PAGE_WRITE : 0) | > + (pte & R_PTE_EAA_X ? PAGE_EXEC : 0); > +} > + > +static int ppc_radix64_get_prot_amr(const PowerPCCPU *cpu) > +{ > + const CPUPPCState *env =3D &cpu->env; > + int amr =3D env->spr[SPR_AMR] >> 62; /* We only care about key0 AMR6= 3:62 */ > + int iamr =3D env->spr[SPR_IAMR] >> 62; /* We only care about key0 IA= MR63:62 */ > + > + return (amr & 0x2 ? 0 : PAGE_WRITE) | /* Access denied if bit is set= */ > + (amr & 0x1 ? 0 : PAGE_READ) | > + (iamr & 0x1 ? 0 : PAGE_EXEC); > +} > + > static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access= _type, > uint64_t pte, int *fault_cause, int *= prot, > int mmu_idx, bool partition_scoped) > diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h > index c5c04a1527..6620b3d648 100644 > --- a/target/ppc/mmu-radix64.h > +++ b/target/ppc/mmu-radix64.h > @@ -3,7 +3,7 @@ > =20 > #ifndef CONFIG_USER_ONLY > =20 > -#include "exec/page-protection.h" > +#ifdef TARGET_PPC64 > =20 > /* Radix Quadrants */ > #define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF > @@ -14,61 +14,10 @@ > #define R_EADDR_QUADRANT2 0x8000000000000000 > #define R_EADDR_QUADRANT3 0xC000000000000000 > =20 > -/* Radix Partition Table Entry Fields */ > -#define PATE1_R_PRTB 0x0FFFFFFFFFFFF000 > -#define PATE1_R_PRTS 0x000000000000001F > - > -/* Radix Process Table Entry Fields */ > -#define PRTBE_R_GET_RTS(rts) \ > - ((((rts >> 58) & 0x18) | ((rts >> 5) & 0x7)) + 31) > -#define PRTBE_R_RPDB 0x0FFFFFFFFFFFFF00 > -#define PRTBE_R_RPDS 0x000000000000001F > - > -/* Radix Page Directory/Table Entry Fields */ > -#define R_PTE_VALID 0x8000000000000000 > -#define R_PTE_LEAF 0x4000000000000000 > -#define R_PTE_SW0 0x2000000000000000 > -#define R_PTE_RPN 0x01FFFFFFFFFFF000 > -#define R_PTE_SW1 0x0000000000000E00 > -#define R_GET_SW(sw) (((sw >> 58) & 0x8) | ((sw >> 9) & 0x7)) > -#define R_PTE_R 0x0000000000000100 > -#define R_PTE_C 0x0000000000000080 > -#define R_PTE_ATT 0x0000000000000030 > -#define R_PTE_ATT_NORMAL 0x0000000000000000 > -#define R_PTE_ATT_SAO 0x0000000000000010 > -#define R_PTE_ATT_NI_IO 0x0000000000000020 > -#define R_PTE_ATT_TOLERANT_IO 0x0000000000000030 > -#define R_PTE_EAA_PRIV 0x0000000000000008 > -#define R_PTE_EAA_R 0x0000000000000004 > -#define R_PTE_EAA_RW 0x0000000000000002 > -#define R_PTE_EAA_X 0x0000000000000001 > -#define R_PDE_NLB PRTBE_R_RPDB > -#define R_PDE_NLS PRTBE_R_RPDS > - > -#ifdef TARGET_PPC64 > - > bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType acces= s_type, > hwaddr *raddr, int *psizep, int *protp, int mmu_i= dx, > bool guest_visible); > =20 > -static inline int ppc_radix64_get_prot_eaa(uint64_t pte) > -{ > - return (pte & R_PTE_EAA_R ? PAGE_READ : 0) | > - (pte & R_PTE_EAA_RW ? PAGE_READ | PAGE_WRITE : 0) | > - (pte & R_PTE_EAA_X ? PAGE_EXEC : 0); > -} > - > -static inline int ppc_radix64_get_prot_amr(const PowerPCCPU *cpu) > -{ > - const CPUPPCState *env =3D &cpu->env; > - int amr =3D env->spr[SPR_AMR] >> 62; /* We only care about key0 AMR6= 3:62 */ > - int iamr =3D env->spr[SPR_IAMR] >> 62; /* We only care about key0 IA= MR63:62 */ > - > - return (amr & 0x2 ? 0 : PAGE_WRITE) | /* Access denied if bit is set= */ > - (amr & 0x1 ? 0 : PAGE_READ) | > - (iamr & 0x1 ? 0 : PAGE_EXEC); > -} > - > #endif /* TARGET_PPC64 */ > =20 > #endif /* CONFIG_USER_ONLY */