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Mon, 07 Oct 2024 23:51:40 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 08 Oct 2024 16:51:36 +1000 Message-Id: Cc: , Subject: Re: [PATCH v3 09/10] target/ppc: simplify var usage in ppc_next_unmasked_interrupt From: "Nicholas Piggin" To: "Harsh Prateek Bora" , , X-Mailer: aerc 0.18.2 References: <20240913041337.912876-1-harshpb@linux.ibm.com> <20240913041337.912876-10-harshpb@linux.ibm.com> In-Reply-To: <20240913041337.912876-10-harshpb@linux.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=npiggin@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote: > As previously done for arch specific handlers, simplify var usage in > ppc_next_unmasked_interrupt by caching the env->pending_interrupts and > env->spr[SPR_LPCR] in local vars and using it later at multiple places. > > Signed-off-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin > --- > target/ppc/excp_helper.c | 54 ++++++++++++++++++++-------------------- > 1 file changed, 27 insertions(+), 27 deletions(-) > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index d0e0f609a0..4eeeedff5b 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -2022,31 +2022,31 @@ static int p9_next_unmasked_interrupt(CPUPPCState= *env, > =20 > static int ppc_next_unmasked_interrupt(CPUPPCState *env) > { > + uint32_t pending_interrupts =3D env->pending_interrupts; > + target_ulong lpcr =3D env->spr[SPR_LPCR]; > + bool async_deliver; > + > #ifdef TARGET_PPC64 > switch (env->excp_model) { > case POWERPC_EXCP_POWER7: > - return p7_next_unmasked_interrupt(env, env->pending_interrupts, > - env->spr[SPR_LPCR]); > + return p7_next_unmasked_interrupt(env, pending_interrupts, lpcr)= ; > case POWERPC_EXCP_POWER8: > - return p8_next_unmasked_interrupt(env, env->pending_interrupts, > - env->spr[SPR_LPCR]); > + return p8_next_unmasked_interrupt(env, pending_interrupts, lpcr)= ; > case POWERPC_EXCP_POWER9: > case POWERPC_EXCP_POWER10: > case POWERPC_EXCP_POWER11: > - return p9_next_unmasked_interrupt(env, env->pending_interrupts, > - env->spr[SPR_LPCR]); > + return p9_next_unmasked_interrupt(env, pending_interrupts, lpcr)= ; > default: > break; > } > #endif > - bool async_deliver; > =20 > /* External reset */ > - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { > + if (pending_interrupts & PPC_INTERRUPT_RESET) { > return PPC_INTERRUPT_RESET; > } > /* Machine check exception */ > - if (env->pending_interrupts & PPC_INTERRUPT_MCK) { > + if (pending_interrupts & PPC_INTERRUPT_MCK) { > return PPC_INTERRUPT_MCK; > } > #if 0 /* TODO */ > @@ -2065,9 +2065,9 @@ static int ppc_next_unmasked_interrupt(CPUPPCState = *env) > async_deliver =3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sr= eset; > =20 > /* Hypervisor decrementer exception */ > - if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { > + if (pending_interrupts & PPC_INTERRUPT_HDECR) { > /* LPCR will be clear when not supported so this will work */ > - bool hdice =3D !!(env->spr[SPR_LPCR] & LPCR_HDICE); > + bool hdice =3D !!(lpcr & LPCR_HDICE); > if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { > /* HDEC clears on delivery */ > return PPC_INTERRUPT_HDECR; > @@ -2075,18 +2075,18 @@ static int ppc_next_unmasked_interrupt(CPUPPCStat= e *env) > } > =20 > /* Hypervisor virtualization interrupt */ > - if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { > + if (pending_interrupts & PPC_INTERRUPT_HVIRT) { > /* LPCR will be clear when not supported so this will work */ > - bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); > + bool hvice =3D !!(lpcr & LPCR_HVICE); > if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { > return PPC_INTERRUPT_HVIRT; > } > } > =20 > /* External interrupt can ignore MSR:EE under some circumstances */ > - if (env->pending_interrupts & PPC_INTERRUPT_EXT) { > - bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); > - bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); > + if (pending_interrupts & PPC_INTERRUPT_EXT) { > + bool lpes0 =3D !!(lpcr & LPCR_LPES0); > + bool heic =3D !!(lpcr & LPCR_HEIC); > /* HEIC blocks delivery to the hypervisor */ > if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && > !FIELD_EX64(env->msr, MSR, PR))) || > @@ -2096,45 +2096,45 @@ static int ppc_next_unmasked_interrupt(CPUPPCStat= e *env) > } > if (FIELD_EX64(env->msr, MSR, CE)) { > /* External critical interrupt */ > - if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { > + if (pending_interrupts & PPC_INTERRUPT_CEXT) { > return PPC_INTERRUPT_CEXT; > } > } > if (async_deliver !=3D 0) { > /* Watchdog timer on embedded PowerPC */ > - if (env->pending_interrupts & PPC_INTERRUPT_WDT) { > + if (pending_interrupts & PPC_INTERRUPT_WDT) { > return PPC_INTERRUPT_WDT; > } > - if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { > + if (pending_interrupts & PPC_INTERRUPT_CDOORBELL) { > return PPC_INTERRUPT_CDOORBELL; > } > /* Fixed interval timer on embedded PowerPC */ > - if (env->pending_interrupts & PPC_INTERRUPT_FIT) { > + if (pending_interrupts & PPC_INTERRUPT_FIT) { > return PPC_INTERRUPT_FIT; > } > /* Programmable interval timer on embedded PowerPC */ > - if (env->pending_interrupts & PPC_INTERRUPT_PIT) { > + if (pending_interrupts & PPC_INTERRUPT_PIT) { > return PPC_INTERRUPT_PIT; > } > /* Decrementer exception */ > - if (env->pending_interrupts & PPC_INTERRUPT_DECR) { > + if (pending_interrupts & PPC_INTERRUPT_DECR) { > return PPC_INTERRUPT_DECR; > } > - if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { > + if (pending_interrupts & PPC_INTERRUPT_DOORBELL) { > return PPC_INTERRUPT_DOORBELL; > } > - if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { > + if (pending_interrupts & PPC_INTERRUPT_HDOORBELL) { > return PPC_INTERRUPT_HDOORBELL; > } > - if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { > + if (pending_interrupts & PPC_INTERRUPT_PERFM) { > return PPC_INTERRUPT_PERFM; > } > /* Thermal interrupt */ > - if (env->pending_interrupts & PPC_INTERRUPT_THERM) { > + if (pending_interrupts & PPC_INTERRUPT_THERM) { > return PPC_INTERRUPT_THERM; > } > /* EBB exception */ > - if (env->pending_interrupts & PPC_INTERRUPT_EBB) { > + if (pending_interrupts & PPC_INTERRUPT_EBB) { > /* > * EBB exception must be taken in problem state and > * with BESCR_GE set.